From: Yongbok Kim
Fix gdbstub to read/write 64 bit FP registers
Signed-off-by: Yongbok Kim
---
target/mips/gdbstub.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 6d1fb70..18e0e6d 100644
--- a/target/mips/gdbstub.c
From: Paul Burton
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton
Signed-off-by: Yongbok Kim
---
hw/mips/mips_malta.c
From: Stefan Markovic
Fix semihosting argument passing for nanoMIPS bare metal
Signed-off-by: Yongbok Kim
---
hw/mips/mips_malta.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index c4139d6..6207d83 100644
--- a/hw/mips
From: James Hogan
nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
read as e.g. 0xbfc1, and prevents writing to the PC clearing
MIPS_HFLAG_M16.
Signed-off-by: James Hogan
Signed-off-by: Yongbok
From: Stefan Markovic
Add I7200 CPU
Reference:
https://www.mips.com/products/warrior/i-class-i7200-multiprocessor-core/
Signed-off-by: Yongbok Kim
---
target/mips/translate_init.inc.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target/mips
From: James Hogan
We shouldn't clear M16 mode when entering an interrupt on nanoMIPS,
otherwise we'll start interpreting the code as normal MIPS code.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
---
target/mips/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --gi
From: Yongbok Kim
Fix ERET/ERETNC can cause ADEL exception
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 6f5e5a3..09ec20a 100644
--- a/target/mips
From: Matthew Fortune
Added very very basic R7 boot code but this is hacked in
unconditionally currently.
Yongbok:
Fix to use right boot loader
Signed-off-by: Yongbok Kim
---
hw/mips/mips_malta.c | 75 +++-
include/elf.h| 1 +
2 files
From: Yongbok Kim
Update BadInstr{P} registers on nanoMIPS
Signed-off-by: Yongbok Kim
---
target/mips/helper.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index e215af9..5299f21 100644
--- a/target
From: Matthew Fortune
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition.
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips
From: James Hogan
ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there
is no ISA bit, so fix set_pc() to skip the hflags update.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/t
From: Yongbok Kim
BadVaddr shouldn't be updated in Debug Mode
Signed-off-by: Yongbok Kim
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 20 +++-
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
= size of the word), and implement gen_align() and a new
gen_ext() based on that. Since we need to know the word size to check
for when the number of bits == the word size, the opc argument is
replaced with a wordsz argument (either 32 or 64).
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
From: Yongbok Kim
Config3.ISAOnExc is read only in nanoMIPS
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 102a039..9946f77 100644
--- a/target/mips
Add nanoMIPS pool32a0 instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 190
1 file changed, 190 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0175a57..0c261c7 100644
--- a/target/mips
From: James Hogan
We shouldn't set the ISA bit in CP0_EPC for nanoMIPS.
Signed-off-by: James Hogan
Signed-off-by: Yongbok Kim
---
target/mips/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 9535131..20
From: Stefan Markovic
Add nanoMIPS CP0_BadInstrX register
Signed-off-by: Stefan Markovic
Signed-off-by: Yongbok Kim
---
target/mips/cpu.h | 1 +
target/mips/helper.c| 6 ++
target/mips/machine.c | 1 +
target/mips/translate.c | 18 ++
4 files changed, 26
Add nanoMIPS p_lsx and LSA instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 139 +++-
1 file changed, 138 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a581330..819cfd9 100644
From: Yongbok Kim
Implement nanoMIPS LLWP and SCWP instruction pair.
Signed-off-by: Yongbok Kim
---
linux-user/mips/cpu_loop.c | 25 ---
target/mips/cpu.h | 2 +
target/mips/helper.h | 2 +
target/mips/op_helper.c| 35 +++
target/mips/translate.c
From: Yongbok Kim
Offset can be larger than 16 bit from nanoMIPS,
and immediate field can be larger than 16 bits as well.
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 60d9287..a581330 100644
--- a
Add nanoMIPS 32bit instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 285 +++-
1 file changed, 284 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4ce80bf..c9b46dd 100644
--- a
Add nanoMIPS branch instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 277
1 file changed, 277 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 08765a7..948d3d5 100644
--- a/target/mips
Add nanoMIPS pool32f floating point instructions.
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 300
1 file changed, 300 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f3a8845..0175a57 100644
--- a
Add nanoMIPS pool16c instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f5b7e14..c1a98da 100644
--- a/target/mips/translate.c
+++ b/target/mips
From: Matthew Fortune
Added a helper for rotx based on the pseudocode from the
arch spec.
Signed-off-by: Yongbok Kim
---
target/mips/helper.h| 2 ++
target/mips/op_helper.c | 94 +
target/mips/translate.c | 15
3 files changed, 111
Add nanoMIPS load and store instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 271
1 file changed, 271 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2e794da..08765a7 100644
--- a/target
From: Matthew Fortune
Add nanoMIPS save and restore instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c1a98da
Add nanoMIPS 16bit load and store instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 110
1 file changed, 110 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 633d0b4..f5b7e14 100644
--- a
Add nanoMIPS decoder.
It covers P16 pool arithmetic and branch instructions.
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 293 +++-
1 file changed, 292 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips
Add nanoMIPS pool32axf instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 94 +
1 file changed, 94 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0c261c7..60d9287 100644
--- a/target/mips
From: Yongbok Kim
Fix to activate microMIPS (and nanoMIPS) on reset when Config3.ISA == {1, 3}
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e57d71e..bfbc300 100644
--- a
Add nanoMIPS 48bit instructions
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 66 +
1 file changed, 66 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c9b46dd..f3a8845 100644
--- a/target/mips
From: Yongbok Kim
Add nanoMIPS OPCODE table
Reference:
nanoMIPS Base ISA Technical Reference Manual
Signed-off-by: Yongbok Kim
---
target/mips/mips-defs.h | 4 +
target/mips/translate.c | 670
2 files changed, 674 insertions(+)
diff --git a
From: Yongbok Kim
Fix to raise a Reserved Instruction exception when given fs is not
available from CTC1.
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 9025f42..41d3634
semihosting argument passing for nanoMIPS bare metal
target/mips: Add I7200 CPU
Yongbok Kim (22):
target/mips: Raise a RI when given fs is n/a from CTC1
target/mips: Fix microMIPS on reset
target/mips: Add nanoMIPS OPCODE table
target/mips: Add decode_nanomips_opc()
target/mips: Add
On 18/06/2018 19:29, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Yongbok Kim transfers duties of QEMU for target MIPS maintainer to
myself as he leaves MIPS. Many thanks to Yongbok for his substantial
contributing to QEMU for MIPS over many years and taking care of its
maintainance
dge.o
common-obj-$(CONFIG_XIO3130) += xio3130_upstream.o xio3130_downstream.o
common-obj-$(CONFIG_IOH3420) += ioh3420.o
Hi Marcel, Philippe.
It looks ok for MIPS Boston.
[Yongbok Kim:
tested for MIPS boston]
Tested-by: Yongbok Kim
Regards,
Yongbok
new @mips.com
address, and get_maintainer.pl in turn reports it when examining git
history. Whilst here add a mapping for my also-defunct
p...@archlinuxmips.org email address too.
Signed-off-by: Paul Burton
Cc: Laurent Vivier
Cc: Michael Tokarev
Cc: Yongbok Kim
Cc: Yongbok Kim
Cc: qemu-devel@nongnu
From: Yongbok Kim
Update my email address to mips.com
Signed-off-by: Yongbok Kim
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1fd7a62..44aa71e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -162,7 +162,7 @@ F: disas
Vivier
Cc: qemu-devel@nongnu.org
Cc: qemu-triv...@nongnu.org
Reviewed-by: Laurent Vivier
[Yongbok Kim:
Updated message subject]
Signed-off-by: Yongbok Kim
---
.mailmap| 1 +
MAINTAINERS | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/.mailmap b/.mailmap
index 28defa1
tags/mips-20171106
for you to fetch changes up to 94d973bdaacb69b034f675fc0fd3f285fea17f94:
MAINTAINERS: Update Paul Burton's email address (2017-11-06 07:36:43 -0800)
MIPS patches 2017-11-06
Changes:
Update email addresses of Yon
tags/mips-20171106
for you to fetch changes up to 94d973bdaacb69b034f675fc0fd3f285fea17f94:
MAINTAINERS: Update Paul Burton's email address (2017-11-06 07:36:43 -0800)
MIPS patches 2017-11-06
Changes:
Update email addresses of Yon
On 30/10/2017 14:20, Peter Maydell wrote:
On 30 October 2017 at 14:09, Yongbok Kim wrote:
On 23/10/2017 15:46, Yongbok Kim wrote:
The following changes since commit
e822e81e350825dd94f41ee2538ff1432b812eb9:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request&
On 23/10/2017 15:46, Yongbok Kim wrote:
The following changes since commit e822e81e350825dd94f41ee2538ff1432b812eb9:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into
staging (2017-10-20 15:04:00 +0100)
are available in the git repository at:
git://
Vivier
Cc: qemu-devel@nongnu.org
Cc: qemu-triv...@nongnu.org
Reviewed-by: Laurent Vivier
[Yongbok Kim:
Updated message subject]
Signed-off-by: Yongbok Kim
---
.mailmap|1 +
MAINTAINERS |2 +-
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/.mailmap b/.mailmap
index
new @mips.com
address, and get_maintainer.pl in turn reports it when examining git
history. Whilst here add a mapping for my also-defunct
p...@archlinuxmips.org email address too.
Signed-off-by: Paul Burton
Cc: Laurent Vivier
Cc: Michael Tokarev
Cc: Yongbok Kim
Cc: Yongbok Kim
Cc: qemu-devel@nongnu
Update my email address to mips.com
Signed-off-by: Yongbok Kim
---
MAINTAINERS |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1217542..245f7d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -162,7 +162,7 @@ F: disas/microblaze.c
-mips.next
MIPS patches 2017-10-23
Changes:
Update email addresses of Yongbok Kim, James Hogan and Paul Burton.
James Hogan (1):
MAINTAINERS: Update James Hog
Update my email address to mips.com
Signed-off-by: Yongbok Kim
---
MAINTAINERS |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9522d1b..726b151 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -162,7 +162,7 @@ F: disas/microblaze.c
x27; targets, remove an unnecessary include.
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
Acked-by: Eduardo Habkost
Signed-off-by: Yongbok Kim
---
hw/mips/Makefile.objs | 2 +-
hw/mips/cputimer.c| 165 --
: James Hogan
Reviewed-by: Eduardo Habkost
Signed-off-by: Yongbok Kim
---
hw/mips/cps.c | 2 +-
hw/mips/mips_fulong2e.c | 2 +-
hw/mips/mips_jazz.c | 2 +-
hw/mips/mips_malta.c| 2 +-
hw/mips/mips_mipssim.c | 2 +-
hw/mips/mips_r4k.c | 2 +-
target/mips/cpu.h | 3
From: Philippe Mathieu-Daudé
no logical change, only code movement (and fix a comment typo).
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
Acked-by: Eduardo Habkost
Signed-off-by: Yongbok Kim
---
target/mips/cp0_timer.c | 1 +
target/mips/cpu.c
From: Philippe Mathieu-Daudé
so it can be used in mips_cpu_realizefn() in the next commit
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Igor Mammedov
Tested-by: James Hogan
Reviewed-by: Eduardo Habkost
Signed-off-by: Yongbok Kim
---
target/mips/internal.h | 1 +
target/mips
Hi,
The patch 1 and 2 contain checkpatch.pl errors but patch 1 is relocating a file
and patch 2 has false positive warnings.
Regards,
Yongbok
The following changes since commit ff5667ed53c544c4dc88dcd7cb23cc509c9a55e0:
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' in
From: Eric Blake
Although none of the existing macro call-sites were broken,
it's always better to write macros that properly parenthesize
arguments that can be complex expressions, so that the intended
order of operations is not broken.
Signed-off-by: Eric Blake
Reviewed-by: Yongbo
, address Eduardo Habkost review]
Tested-by: James Hogan
Reviewed-by: Eduardo Habkost
Signed-off-by: Yongbok Kim
---
target/mips/cpu-qom.h| 1 +
target/mips/cpu.c| 50 -
target/mips/internal.h | 59
Hogan
Reviewed-by: Eduardo Habkost
Signed-off-by: Yongbok Kim
---
target/mips/cpu.c | 3 +++
target/mips/translate.c | 1 -
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 68bf423..e3ef835 100644
--- a/target/mips/cpu.c
+++ b/target
)
>
> -#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
> - ((uint64_t)b << 32) | \
> - ((uint64_t)c << 16) | \
> - (uint64_t)d)
> -#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
> +#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)(a) << 48) |\
> + ((uint64_t)(b) << 32) |\
> + ((uint64_t)(c) << 16) |\
> + (uint64_t)(d))
> +#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)(a) << 32) |
> (uint64_t)(b))
> #endif
>
> /** DSP Arithmetic Sub-class insns **/
>
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 14/09/2017 15:16, Sergey Smolov wrote:
>
> On 14.09.2017 16:58, Peter Maydell wrote:
>> At translate time it is generating some extra code which at runtime
>> will call the helper_trace_reg_access() function, passing it the
>> values in the registers at this point. This will result in poor
>>
On 13/09/2017 12:01, Peter Maydell wrote:
> On 13 September 2017 at 08:29, Sergey Smolov wrote:
>> -d options are a bit high-level for me, because I just see the execution
>> result for every instruction. So it will be a mistake to think that every
>> change of some register's value is just a ne
On 01/09/2017 17:09, Philippe Mathieu-Daudé wrote:
> On 09/01/2017 12:48 PM, Eduardo Habkost wrote:
>> On Fri, Sep 01, 2017 at 12:44:42PM -0300, Philippe Mathieu-Daudé wrote:
>>> On 09/01/2017 12:18 PM, Eduardo Habkost wrote:
On Wed, Aug 30, 2017 at 07:52:18PM -0300, Philippe Mathieu-Daudé w
On 08/08/2017 16:43, Philippe Mathieu-Daudé wrote:
> On 08/08/2017 09:15 AM, Philippe Mathieu-Daudé wrote:
>> probably incorrect copy/paste from 8d162c2b68db72623a507069fda0e35ccd1c6b85
>
> incorrect since 10 years, so can wait 2.11 :P
Fair enough :)
Regards,
Yongbok
insn_flags = CPU_MIPS32,
> .mmu_type = MMU_TYPE_FMT,
> },
> {
>
Reviewed-by: Yongbok Kim
Regards,
Yongbok
78
("target/arm: use DISAS_EXIT for eret handling").
Fixes: e350d8ca3ac7 ("target/mips: optimize indirect branches")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Yongbok Kim
Cc: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
f-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Paolo Bonzini
Cc: k...@vger.kernel.org
Reviewed-by: Richard Henderson
[Yongbok Kim:
minor change]
Signed-off-by: Yongbok Kim
---
hw/mips/addr.c| 12
hw/mips/mips_malta.c | 19 ---
include/hw/
gned (int32_t) types.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Paolo Bonzini
Cc: k...@vger.kernel.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yongbok Kim
---
target/mips/helper.c | 23 +++
1 file changed, 11 insertions(+), 12 delet
Jarno
Cc: Yongbok Kim
Reviewed-by: Yongbok Kim
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 51626ae..0bca700 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
ned-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ba6b8f5..bcea2a1 100644
--- a/t
ed.
Fixes: 2e70f6efa8b9 ("Add instruction counter.")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Yongbok Kim
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/mips/trans
nds to 128kiB in memory.
Therefore reserve 128kiB after the initrd.
Signed-off-by: Aurelien Jarno
Tested-by: Yongbok Kim
Signed-off-by: Yongbok Kim
---
hw/mips/mips_malta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
in
The following changes since commit aaaec6acad7cf97372d48c1b09126a09697519c8:
Update version for v2.10.0-rc1 release (2017-08-02 16:36:32 +0100)
are available in the git repository at:
git://github.com/yongbok/upstream-qemu.git tags/mips-20170803
for you to fetch changes up to d673a68db6963e
From: Leon Alrae
PFN0 and PFN1 have to be masked out with PageMask_Mask.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
[Yongbok Kim:
Added commit message]
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a
On 02/08/2017 19:56, Philippe Mathieu-Daudé wrote:
> Hi Leon,
>
> On 08/02/2017 10:58 AM, Yongbok Kim wrote:
>> From: Leon Alrae
>>
>> PFN0 and PFN1 have to be masked out with PageMask_Mask.
>>
>> Signed-off-by: Leon Alrae
>> Reviewed-by: Yon
From: Leon Alrae
PFN0 and PFN1 have to be masked out with PageMask_Mask.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
[Yongbok Kim:
Added commit message]
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a
ned-off-by: Aurelien Jarno
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Yongbok Kim
---
hw/mips/mips_fulong2e.c | 15 +--
hw/mips/mips_malta.c| 14 --
hw/mips/mips_mipssim.c | 5 +++--
hw/mips/mips_r4k.c | 6 --
4 fil
The following changes since commit 871a0f7ad2b9560c5f7d640125c5be95ca23ca7f:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170728' into
staging (2017-07-28 10:35:02 +0100)
are available in the git repository at:
git://github.com/yongbok/upstream-qemu.git tags/mips-20170728
for
big_endian=0.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Aurelien Jarno
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yongbok Kim
---
hw/core/loader.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index c17ace0..e5e8cbb 100644
--- a/hw/cor
NTAINERS
> @@ -182,6 +182,7 @@ F: include/hw/intc/mips_gic.h
> F: include/hw/timer/mips_gictimer.h
> F: tests/tcg/mips/
> F: disas/mips.c
> +F: default-configs/mips*-softmmu.mak
>
> Moxie
> M: Anthony Green
>
Acked-by: Yongbok Kim
Regards,
Yongbok
On 26/07/2017 05:13, Philippe Mathieu-Daudé wrote:
> Hi John,
>
> On 07/25/2017 07:55 PM, Programmingkid wrote:
>> While compiling the mips64el-softmmu target I encountered these errors:
>>
>>CC hw/display/g364fb.o
>> hw/core/loader-fit.c:105:41: error: expected expression
>> *
m to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Reviewed-by: Yongbok Kim
Signed-off-by: Yongbok Kim
---
target/mips/cpu.h
don't persist
between ERL=0 and ERL=1.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
[yongbok@imgtec.com:
cosmetic changes]
Signed-off-by: Yongbok Kim
---
target/mips/cpu.h | 17 +
target/mips/op_helper.c | 10 ++
2 files changed, 23
From: James Hogan
Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
configuration, along with the related Segmentation Control (SC) feature
and writable CP0_EBase.WG bit.
This allows it to run Malta EVA kernels.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc
From: James Hogan
Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic
CPUs. This allows 64-bit guests to run KVM itself, which uses
CP0_EBase.WG to point CP0_EBase at XKPhys.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Reviewed-by: Yongbok Kim
Signed-off
n the tlb flushes in these cases to only flush the QEMU
TLB.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Tested-by: Yongbok Kim
Signed-off-by: Yongbok Kim
---
target/mips/helper.c| 2 +-
target/mips/op_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
then override
the mem_idx used for the operation.
Unfortunately some Loongson 2E instructions use overlapping encodings,
so we must be careful not to prevent those from being decoded when EVA
is absent.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Reviewed-by: Yongbok Kim
Signed
not exposed to the guest).
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Reviewed-by: Yongbok Kim
[yongbok@imgtec.com:
cosmetic changes]
Signed-off-by: Yongbok Kim
---
target/mips/helper.c | 191 ---
1 file changed, 152
when a new MMU
mode is added.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
Signed-off-by: Yongbok Kim
---
target/mips/cpu.h | 8 +++-
target/mips/op_helper.c | 4 ++--
target/mips/translate.c | 2 +-
3 files changed, 10 insertions(+), 4 deletions(-)
diff
y longer. This should be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
Signed-off-by: Yongbok Kim
---
target
* helpers used
for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and
gen_st_cond().
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Yongbok Kim
Cc: Aurelien Jarno
Signed-off-by: Yongbok Kim
---
target/mips/translate.c | 77
fields to TLB entry")
Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support")
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Tested-by: Yongbok Kim
[yongbok@imgtec.com:
cosmetic changes]
Signed-off-by: Yongbok Kim
---
target/mips/op_helper.c | 12 +++
Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Reviewed-by: Yongbok Kim
[yongbok@imgtec.com:
minor changes]
Signed-off-by: Yongbok Kim
---
target/mips/cpu.h| 5 -
target/mips/helper.c | 14 --
target/mips/machine.c| 6 +++---
target/mips/op_helper.c
The following changes since commit 25d0233c1ac6cd14a15fcc834f1de3b179037b1d:
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20170720-pull-request'
into staging (2017-07-20 16:40:01 +0100)
are available in the git repository at:
git://github.com/yongbok/upstream-qemu.git tags/mips-2017
From: James Hogan
Implement decoding of microMIPS EVA load and store instruction groups in
the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond()
helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as
opc.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc
ext32s_tl to
sign extend it, as done for various other target_ulong COP0 registers.
Fixes: d279279e2b5c ("target-mips: implement UserLocal Register")
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Petar Jovanovic
Reviewed-by: Yongbok Kim
Signed-off-by: Y
he shadow half of the TLB.
>
> Therefore weaken the tlb flushes in these cases to only flush the QEMU
> TLB.
>
> Signed-off-by: James Hogan
> Cc: Yongbok Kim
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - New patch.
> ---
> target/mips/helper.c| 2 +-
&g
n these bits are set.
>
> Fixes: 2fb58b73746e ("target-mips: add RI and XI fields to TLB entry")
> Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support")
> Signed-off-by: James Hogan
> Cc: Yongbok Kim
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - New
On 18/07/2017 12:55, James Hogan wrote:
> Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic
> CPUs. This allows 64-bit guests to run KVM itself, which uses
> CP0_EBase.WG to point CP0_EBase at XKPhys.
>
> Signed-off-by: James Hogan
> Cc: Yongbok Kim
&g
which should be set
> up even when the feature is not exposed to the guest).
>
> Signed-off-by: James Hogan
> Cc: Yongbok Kim
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - Use hwaddr instead of target_ulong for physical addresses in
> get_seg[ctl]_physical_add
XKPhys, and possibly out of range of KSEG0 and KSEG1.
>
> Signed-off-by: James Hogan
> Cc: Yongbok Kim
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - Fix CP0_EBase.WG to be read only when WG is not set in
> CP0_EBase_rw_bitmask, otherwise it will be wrongly probed as p
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