[Qemu-devel] [PATCH] target/riscv: fix counter-enable checks in ctr()

Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang --- target/riscv/csr.c | 12 +--- 1 file changed, 9 insertions

[Qemu-devel] [PATCH v2 2/2] hw/openrisc: avoid undefined shift in openrisc_pic_cpu_handler()

In C99 signed shift (1 << 31) is undefined behavior, since the result exceeds INT_MAX. Use 1U instead and move the shift after the check. Cc: Jia Liu Cc: Paolo Bonzini Signed-off-by: Xi Wang --- hw/openrisc/pic_cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --gi

[Qemu-devel] [PATCH v2 1/2] hw/openrisc: fix masking in openrisc_pic_cpu_handler()

t necessary for masking. Simply use (cpu->env.picsr & cpu->env.picmr). Cc: Jia Liu Cc: Paolo Bonzini Signed-off-by: Xi Wang --- hw/openrisc/pic_cpu.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c i

[Qemu-devel] [PATCH] target-or32: fix masking in openrisc_pic_cpu_handler()

A correct mask should be `x & (1 << i)', rather than `x && (1 << i)'. Also, in C99 signed shift (1 << 31) is undefined behavior, since the result exceeds INT_MAX; use 1U instead. Signed-off-by: Xi Wang --- hw/openrisc_pic.c |8 +--- 1 file change