You will need to apply the patch from
https://bugs.launchpad.net/qemu/+bug/1696353 to run this sample app on
current master.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1696773
Title:
golang call
Public bug reported:
An example program can be found here:
https://github.com/willnewton/qemucrash
This code starts a goroutine (thread) and calls exec repeatedly. This
works ok natively but when run under ARM user emulation it segfaults
(usually, there are occasionally other failures).
** Affe
True, but it used to work albeit with slightly wrong semantics. It now
fails hard even though the golang runtime doesn't make any use of Sys V
semaphores so the presence of the flag is not noticeable by any normal
user.
--
You received this bug notification because you are a member of qemu-
devel
Public bug reported:
With current master golang binaries fail when run under linux-user, for
example:
[will@localhost qemu]$ ./arm-linux-user/qemu-arm glide
runtime: failed to create new OS thread (have 2 already; errno=22)
fatal error: newosproc
runtime stack:
runtime.throw(0x45f879, 0x9)
This series adds support for the AArch32 CRC32 instructions added in
ARMv8.
Will Newton (2):
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
configure | 2 +-
include/qemu/crc32c.h | 4 ++--
target
for the linux-user binary.
Signed-off-by: Will Newton
---
configure | 2 +-
target-arm/cpu.c | 1 +
target-arm/cpu.h | 1 +
target-arm/helper.c| 39 +++
target-arm/helper.h| 3 +++
target-arm/translate.c | 56
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Changes in v4:
- None
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8.
The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ensure it is linked for the linux-user binary.
Signed-off-by: Will Newton
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Changes in v3:
- None
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include
This series adds support for the AArch32 CRC32 instructions added in
ARMv8.
Will Newton (2):
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
configure | 2 +-
include/qemu/crc32c.h | 4 ++--
target
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8.
The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ensure it is linked for the linux-user binary.
Signed-off-by: Will Newton
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include/qemu/crc32c.h
@@ -25,8
This series adds support for the AArch32 CRC32 instructions added in
ARMv8.
Will Newton (2):
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
configure | 2 +-
include/qemu/crc32c.h | 4 ++--
target
Add a table-driven CRC-32 implementation similar in style to the
existing CRC-32C implementation.
Signed-off-by: Will Newton
---
include/qemu/crc32.h | 15
util/Makefile.objs | 1 +
util/crc32.c | 98
3 files changed, 114
This series adds support for the AArch32 CRC32 instructions added in
ARMv8. The CRC-32 algorithm is added alongside the existing CRC-32C
implementation which requires a small fix to the crc32c.h header file.
Will Newton (3):
include/qemu/crc32c.h: Rename include guards to match filename
util
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/helper.c| 37 +
target-arm/helper.h| 3 +++
target-arm/translate.c | 48
3 files changed
Signed-off-by: Will Newton
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include/qemu/crc32c.h
@@ -25,8 +25,8 @@
*
*/
-#ifndef
Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 74 ++
1 file changed, 56 insertions(+), 18 deletions(-)
Changes in v3
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9eb5b92..c179817
Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 62 ++
1 file changed, 48 insertions(+), 14 deletions(-)
diff --git a
This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/helper.c | 17 +
target-arm
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 53 +-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm
Add support for the AArch32 floating-point VRINTX instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
Changes in v2:
- Move code outside the arms of the if
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
Changes in v2:
- Merge VRINTZ handling into the
Add support for the AArch32 floating-point VRINTZ instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 16
1 file changed, 16 insertions(+)
Changes in v2:
- Move code outside the arms of the if
diff --git a/target-arm/translate.c b/target-arm/translate.c
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 61 ++
1 file changed, 61 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
Add support for the AArch32 floating-point VRINTR instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
Changes in v2:
- Move code outside the arms of the if
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 54 ++
1 file changed, 54 insertions(+)
Changes in v2:
- Add comment to fp_decode_rm lookup table
diff
This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.
Signed-off-by: Will Newton
Reviewed-by:
This series adds support for the floating-point and Advanced SIMD
versions of the VRINT family of instructions.
Will Newton (9):
target-arm: Move arm_rmode_to_sf to a shared location.
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
target-arm: Add support for AArch32 FP VRINTR
This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.
Signed-off-by: Will Newton
---
targe
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5108f6b..b6d11db 100644
--- a/target-arm
Add support for the AArch32 floating-point VRINTR instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f688f6d..73e0e8d 100644
--- a/target-arm/translate.c
+++ b
Add support for the AArch32 floating-point VRINTX instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 153d0e6..5108f6b 100644
--- a/target-arm/translate.c
+++ b
Add support for the AArch32 Advanced SIMD VRINTZ instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b6d11db..16242d3 100644
--- a/target
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
and VRINTM instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.
Signed-off-by: Will Newton
---
target-arm/helper.c | 17 +
target-arm/helper.h | 1 +
2 files
Add support for the AArch32 floating-point VRINTZ instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 73e0e8d..153d0e6 100644
--- a/target-arm
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
The regs parameter is not used anywhere, so remove it.
Signed-off-by: Will Newton
---
linux-user/elfload.c | 3 +--
linux-user/flatload.c | 3 +--
linux-user/linuxload.c | 4 ++--
linux-user/qemu.h | 6 ++
4 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/linux-user
t;
> So, if you can point me to any arm model which can do usb passthrough
> I would be very happy. Thanks.
Just a word of warning - the Raspberry Pi uses a non-standard (i.e.
non-EHCI) USB host controller so it may prove very difficult to get
USB working.
--
Will Newton
Toolchain Working Group, Linaro
Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from IEEE 754-2008. They are
similar to min() and max() but differ in the handling of QNaN arguments.
Signed-off-by: Will Newton
---
fpu/softfloat.c | 32
The nan_exp argument is not used, so remove it.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
fpu/softfloat.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 7ba51b6..97bf627 100644
--- a/fpu/softfloat.c
+++ b/fpu
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/helper.c| 25 +
target-arm/helper.h| 5 +
target-arm/translate.c | 50
This series adds support for three new instructions added in ARMv8 -
VSEL, VMINNM and VMAXNM.
Will Newton (6):
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
target-arm: Implement ARMv8 VSEL instruction.
softfloat: Remove unused argument from MINMAX macro.
softfloat
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
Changes in v8:
- Use VFP helper instead of adding a NEON specific one
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/translate.c | 32 +++-
1 file changed, 27 insertions
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/translate.c | 135 -
1 file changed, 134 insertions(+), 1 deletion(-)
diff --git a
Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from IEEE 754-2008. They are
similar to min() and max() but differ in the handling of QNaN arguments.
---
fpu/softfloat.c | 54 +
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
---
target-arm/translate.c | 135 -
1 file changed, 134 insertions(+), 1 deletion(-)
Changes in v7:
- Break out VSEL handling into a function
- Properly
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/helper.h | 3 +++
target-arm/neon_helper.c | 16
target-arm/translate.c | 31 ++-
3 files changed, 41 insertions(+), 9
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
---
target-arm/helper.c| 25 +
target-arm/helper.h| 5 +
target-arm/translate.c | 50 ++
3 files changed, 80 insertions(+)
Changes in
The nan_exp argument is not used, so remove it.
---
fpu/softfloat.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Changes in v7:
- New patch
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 7ba51b6..97bf627 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6706,7 +6706,7
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
---
target-arm/translate.c | 32 +++-
1 file changed, 27 insertions(+), 5 deletions(-)
Changes in v7:
- Fix comment style
- F
This series adds support for three new instructions added in ARMv8 -
VSEL, VMINNM and VMAXNM.
Will Newton (6):
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
target-arm: Implement ARMv8 VSEL instruction.
softfloat: Remove unused argument from MINMAX macro.
softfloat
On 29 November 2013 15:26, Peter Maydell wrote:
> On 28 November 2013 17:07, Will Newton wrote:
>>
>> Floating point is an extension to the instruction set rather than
>> a coprocessor, so call it directly from the ARM and Thumb decode
>> functions.
>
> Hi;
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/helper.h | 3 +++
target-arm/neon_helper.c | 24
target-arm/translate.c | 23 +--
3 files changed, 44 insertions(+), 6
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 130 -
1 file changed, 129 insertions(+), 1 deletion(-)
Changes in v6:
- None
diff --git a
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
Changes in
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/helper.c| 41 +
target-arm/helper.h| 5 +
target-arm/translate.c | 43 +++
3
On 15 October 2013 16:09, Will Newton wrote:
>
> Floating point is an extension to the instruction set rather than
> a coprocessor, so call it directly from the ARM and Thumb decode
> functions.
>
> Signed-off-by: Will Newton
> ---
> tar
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 130 -
1 file changed, 129 insertions(+), 1 deletion(-)
Changes in v5:
- Break out VSEL decode
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
Changes in
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 113 +
1 file changed, 113 insertions(+)
Changes in v4:
- Fix leak of temporaries
- Extend
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target
On 3 October 2013 15:34, Richard Henderson wrote:
> On 10/03/2013 05:51 AM, Will Newton wrote:
>> +case 0: /* eq: Z */
>> +tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF,
>> zero,
>> +
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 115 ++---
1 file changed, 110 insertions(+), 5 deletions(-)
Changes in v3:
- Move calls to
On 3 October 2013 13:59, Peter Maydell wrote:
> On 3 October 2013 21:51, Will Newton wrote:
>>
>> This adds support for the VSEL floating point selection instruction
>> which was added in ARMv8. It is based on the previous patch[1] from
>> Mans Rullgard, but attem
-by: Will Newton
---
target-arm/translate.c | 105 +
1 file changed, 105 insertions(+)
Changes in v2:
- Integrate vsel decoding into disas_vfp_insn
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..5e49334 100644
--- a
: Will Newton
---
target-arm/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..7bfd606 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2617,6
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