> On Jul 4, 2019, at 08:45, Philippe Mathieu-Daudé wrote:
>
> Cc'ing PPC/taihu_405ep and ARM/Digic4 maintainers.
>
> On 7/3/19 6:36 PM, Philippe Mathieu-Daudé wrote:
>> On 7/3/19 6:20 PM, Stephen Checkoway wrote:
>>>> On Jul 3, 2019, at 12:02, Philippe
> On Jul 3, 2019, at 12:02, Philippe Mathieu-Daudé wrote:
>
> On 7/3/19 5:52 PM, Stephen Checkoway wrote:
>>
>>
>>> On Jul 1, 2019, at 20:59, Philippe Mathieu-Daudé wrote:
>>>
>>> Parallel NOR flashes are limited to 16-bit bus accesses.
&g
aque, hwaddr offset,
> uint64_t value,
> static const MemoryRegionOps pflash_cfi02_ops = {
> .read = pflash_read,
> .write = pflash_write,
> +.impl.max_access_size = 2,
> .valid.min_access_size = 1,
> .valid.max_access_size = 4,
> .endianness = DEVICE_NATIVE_ENDIAN,
> --
> 2.20.1
>
--
Stephen Checkoway
"offset:0x%04"PRIx64" width:%d value:0x%0*x
> cmd:0x%02x wcycle:%u"
> +pflash_io_write(uint64_t offset, int width, int fmt_width, uint32_t value,
> uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x wcycle:%u"
> pflash_data_read8(uint64_t offset, uint32_t value) "data offset:0x%04"PRIx64"
> value:0x%02x"
> pflash_data_read16(uint64_t offset, uint32_t value) "data
> offset:0x%04"PRIx64" value:0x%04x"
> pflash_data_read32(uint64_t offset, uint32_t value) "data
> offset:0x%04"PRIx64" value:0x%08x"
> --
> 2.20.1
>
Either way,
Signed-off-by: Stephen Checkoway
(And please let me know if I'm doing code review incorrectly or if that should
be Reviewed-by or whatever.)
Cheers,
Steve
--
Stephen Checkoway
> On Jun 25, 2019, at 04:32, Markus Armbruster wrote:
>
> Stephen Checkoway writes:
>
>>> On Jun 24, 2019, at 12:05, Philippe Mathieu-Daudé wrote:
>>>
>>>> On 6/22/19 2:25 PM, Philippe Mathieu-Daudé wrote:
>>>> Hi Stephen,
>>>
> On Jun 24, 2019, at 12:05, Philippe Mathieu-Daudé wrote:
>
>> On 6/22/19 2:25 PM, Philippe Mathieu-Daudé wrote:
>> Hi Stephen,
>>
>> This series haven't fall through the cracks, however it is taking me
>> longer than expected to review it.
>
as well.
Since guest firmware can use status bits DQ7, DQ6, DQ3, and DQ2 to
determine the current state of sector erasure, these bits are properly
implemented.
Signed-off-by: Stephen Checkoway
Acked-by: Thomas Huth
---
hw/block/pflash_cfi02.c | 153
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
Signed-off-by: Stephen Chec
.
Signed-off-by: Stephen Checkoway
Acked-by: Thomas Huth
---
hw/block/pflash_cfi02.c | 94 +++
tests/pflash-cfi02-test.c | 59 ++--
2 files changed, 131 insertions(+), 22 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block
ach
device.)
Testing is limited to 16-bit wide devices due to the current inability
to override the properties set by `pflash_cfi02_register`, but multiple
configurations are tested.
Stop using global_qtest. Instead, package the qtest variable inside the
FlashConfig structure.
Signed-off-by: Stephen
would make testing currently
impossible.
Signed-off-by: Stephen Checkoway
Acked-by: Thomas Huth
---
hw/block/pflash_cfi02.c | 177 +---
tests/pflash-cfi02-test.c | 185 --
2 files changed, 265 insertions(+), 97 deletions
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
Acked-by: Thomas Huth
---
hw/block/pflash_cfi02.c | 21
.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 221 +---
1 file changed, 95 insertions(+), 126 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index f2c6201f81..4b7af71806 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
Acked-by: Thomas Huth
---
hw/block
is on going.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index be10036886..cb1160eb35 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen Checkoway
---
tests
.
Changes from v3:
- Replace err.h/err() with glib functions; and
- Reformat qtest_initf lines.
Stephen Checkoway (10):
block/pflash_cfi02: Add test for supported commands
block/pflash_cfi02: Refactor, NFC intended
block/pflash_cfi02: Fix command address comparison
block/pflash_cfi02: Implement
> On Apr 18, 2019, at 08:13, Philippe Mathieu-Daudé wrote:
>
> On 4/17/19 2:50 AM, Stephen Checkoway wrote:
>> The SCC/ESCC will briefly stop asserting an interrupt when the
>> transmit FIFO is filled.
>>
>> This code doesn't model the transmit FIFO/shi
ently
pending.
Signed-off-by: Stephen Checkoway
Reviewed-by: Philippe Mathieu-Daudé
---
I added a sentence about the Z85C30 necessitating this to the commit message.
hw/char/escc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 628f5f81f7..c5b05
sector length and number of sectors
- erase suspend supported
--
Stephen Checkoway
> On Apr 18, 2019, at 00:47, Thomas Huth wrote:
>
> On 18/04/2019 00.01, Stephen Checkoway wrote:
>> Test the AMD command set for parallel flash chips. This test uses an
>> ARM musicpal board with a pflash drive to test the following list of
>> currently-supporte
is on going.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index be10036886..cb1160eb35 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
ach
device.)
Testing is limited to 16-bit wide devices due to the current inability
to override the properties set by `pflash_cfi02_register`, but multiple
configurations are tested.
Stop using global_qtest. Instead, package the qtest variable inside the
FlashConfig structure.
Signed-off-by: Stephen
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 8
.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 94 +++
tests/pflash-cfi02-test.c | 59 ++--
2 files changed, 131 insertions(+), 22 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index cb1160eb35
as well.
Since guest firmware can use status bits DQ7, DQ6, DQ3, and DQ2 to
determine the current state of sector erasure, these bits are properly
implemented.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 153 ++
tests/pflash-cfi02-test.c
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
Signed-off-by: Stephen Chec
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen Checkoway
---
tests
would make testing currently
impossible.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 177 +---
tests/pflash-cfi02-test.c | 185 --
2 files changed, 265 insertions(+), 97 deletions(-)
diff --git a/hw/block
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 21 +
tests/pflash
.
Stephen Checkoway (10):
block/pflash_cfi02: Add test for supported commands
block/pflash_cfi02: Refactor, NFC intended
block/pflash_cfi02: Fix command address comparison
block/pflash_cfi02: Implement intereleaved flash devices
block/pflash_cfi02: Implement nonuniform sector sizes
block
.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 221 +---
1 file changed, 95 insertions(+), 126 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index f2c6201f81..4b7af71806 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw
escc_update_irq(s);
which appears to do the right thing in my tests.
Thank you,
Steve
--
Stephen Checkoway
erted, no additional interrupts will
ever fire.
This fixes that situation by explicitly lowering the IRQ when a
character is written to the buffer and no other interrupts are currently
pending.
Signed-off-by: Stephen Checkoway
---
hw/char/escc.c | 7 +++
1 file changed, 7 insertions(+)
diff
On Apr 10, 2019, at 16:01, Philippe Mathieu-Daudé wrote:
> On 3/6/19 12:01 PM, Paolo Bonzini wrote:
>> On 05/03/19 06:10, Stephen Checkoway wrote:
>>> The SCC/ESCC will briefly stop asserting an interrupt when the
>>> transmit FIFO is filled.
>>>
>>&
that it is using unlock addresses 0x
and 0x2AAA. My guess is this reflects a bug in some firmware and it should be
using 0x555 and 0x2AA. I haven't seen any AMD pflash chips that used other
unlock addresses, but I've only looked at about a dozen part sheets and I'm not
sure w
Hi Phil,
> On Apr 9, 2019, at 06:34, Philippe Mathieu-Daudé wrote:
>
> Hi Stephen,
>
> [Cc'ing Markus and Laszlo, we have similar interest in pflash01 testing]
>
> On 4/8/19 10:55 PM, Stephen Checkoway wrote:
>> The goal of this patch series impleme
qtest in there. The earlier
patches would still use global_qtest. Would that be acceptable or would you
prefer that global_qtest not appear in any of the patches?
Or rather than putting it in the FlashConfig struct, I could just pass a
separate parameter around. Whatever you prefer.
--
Stephen Checkoway
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
Signed-off-by: Stephen Chec
as well.
Since guest firmware can use status bits DQ7, DQ6, DQ3, and DQ2 to
determine the current state of sector erasure, these bits are properly
implemented.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 153 ++
tests/pflash-cfi02-test.c
would make testing currently
impossible.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 177 ++---
tests/pflash-cfi02-test.c | 179 +-
2 files changed, 265 insertions(+), 91 deletions(-)
diff --git a/hw/block
.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 94 +++
tests/pflash-cfi02-test.c | 59 ++--
2 files changed, 131 insertions(+), 22 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index cb1160eb35
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 21 +
tests/pflash
.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 221 +---
1 file changed, 95 insertions(+), 126 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index f2c6201f81..4b7af71806 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw
ach
device.)
Testing is limited to 16-bit wide devices due to the current inability
to override the properties set by `pflash_cfi02_register`, but multiple
configurations are tested.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 270 +---
tests/pflash-cfi02-te
is on going.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index be10036886..cb1160eb35 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 8
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen Checkoway
---
tests
behavior,
probably due to a bug in the firmware itself.
Changes from v1:
- Fix missing spaces around *, -, and ?.
- Fix missing Signed-off-by line on patch 7
- Replace use of errc with g_printerr and exit
Stephen Checkoway (10):
block/pflash_cfi02: Add test for supported commands
block
.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 94 +++
tests/pflash-cfi02-test.c | 59 ++--
2 files changed, 131 insertions(+), 22 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index fa6929b9b6
From: Stephen Checkoway
Simplify and refactor for upcoming commits. In particular, pull out all
of the code to modify the status into simple helper functions. Status
handling becomes more complex once multiple chips are interleaved to
produce a single device.
No change in functionality is
as well.
Since guest firmware can use status bits DQ7, DQ6, DQ3, and DQ2 to
determine the current state of sector erasure, these bits are properly
implemented.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 153 ++
tests/pflash-cfi02-test.c
From: Stephen Checkoway
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
---
hw/block
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
Signed-off-by: Stephen Chec
ach
device.)
Testing is limited to 16-bit wide devices due to the current inability
to override the properties set by `pflash_cfi02_register`, but multiple
configurations are tested.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 270 +---
tests/pflash-cfi02-te
From: Stephen Checkoway
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen
When the flash device is performing a chip erase, all commands are
ignored. When it is performing a sector erase, only the erase suspend
command is valid, which is currently not supported.
In particular, the reset command should not cause the device to reset to
read array mode while programming is
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 21 +
tests/pflash
would make testing currently
impossible.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 177 ++---
tests/pflash-cfi02-test.c | 181 +-
2 files changed, 266 insertions(+), 92 deletions(-)
diff --git a/hw/block
behavior,
probably due to a bug in the firmware itself.
Stephen Checkoway (10):
block/pflash_cfi02: Add test for supported commands
block/pflash_cfi02: Refactor, NFC intended
block/pflash_cfi02: Fix command address comparison
block/pflash_cfi02: Implement intereleaved flash devices
block
On Apr 1, 2019, at 21:28, Richard Henderson
wrote:
> Thanks. We should probably update our submodule to the v4 release as well.
Is that something that you want with this patch?
--
Stephen Checkoway
Starting with version 4 of capstone, the header files live in the
`$prefix/include/capstone` directory.
This modifies the configure script to check for if
cannot be found.
Signed-off-by: Stephen Checkoway
---
configure| 9 +
include/disas/capstone.h | 4
2 files
> On Mar 6, 2019, at 04:38, Laurent Vivier wrote:
>
> Applied to my trivial-patches branch.
Great, thanks!
Cheers,
Steve
erted, no additional interrupts will
ever fire.
This fixes that situation by explicitly lowering the IRQ when a
character is written to the buffer.
Signed-off-by: Stephen Checkoway
---
hw/char/escc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 628f5
e vast majority of x86 instructions access at most one segment,
but off-hand, I can think of a handful that access two:
- movs
- cmps
- push r/m32
- pop r/m32
- call m32
- call m16:m32
I'm not sure if there are others.
--
Stephen Checkoway
to store 64-bits of data. If this store happens
starting 4 bytes before the end of the segment, I believe this should either
case #GP(0) or #SS(0), depending on the segment. But if the 64-bit store is
broken into two 32-bit stores, the first may succeed and the second fail,
leading to an inconsistent state. Do you have any thoughts on how this should
be handled?
Thank you,
Steve
--
Stephen Checkoway
roadly acceptable and
the functionality is desired.
If not, thank you Peter for answering my questions which enabled me to solve my
problem.
Cheers,
Steve
> On Feb 24, 2019, at 15:21, Stephen Checkoway
> wrote:
>
>
>
>> On Feb 24, 2019, at 14:46, Peter Maydell wrote:
> On Feb 24, 2019, at 14:46, Peter Maydell wrote:
>
> On Sun, 24 Feb 2019 at 19:37, Stephen Checkoway
> wrote:
>> I think that something about adding the tcg_gen_brcond_tl is causing values
>> to become dead and then qemu aborts.
>
> Yep -- all "TCG temp
}
for (i = 0; i < 4; ++i) {
@@ -8482,6 +8515,7 @@ static void i386_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
dc->T0 = tcg_temp_new();
dc->T1 = tcg_temp_new();
dc->A0 = tcg_temp_new();
+dc->A1 = tcg_temp_new();
dc->tmp0 = tcg_temp_new();
dc->tmp1_i64 = tcg_temp_new_i64();
--
Stephen Checkoway
k/pflash_cfi02.c#L154> and
here <https://github.com/qemu/qemu/blob/master/hw/block/pflash_cfi02.c#L279>).
If the chip size isn't a power of two, this breaks.
--
Stephen Checkoway
ed (build-time constant).
Gotcha, thanks for the info. It sounds like the code for the Intel command set
chips (cfi01) and the AMD command set chips (cfi02) have different requirements
for their use.
Regards,
Steve
--
Stephen Checkoway
hub.com/qemu/qemu/compare/master...stevecheckoway:pflash02#diff-d33881bd0ef099e2f46ebd4797c653bcR738>.)
Cheers,
Steve
--
Stephen Checkoway
are sector groups that can be
locked/unlocked using high voltage. It seems easy enough to model this by
configuring sectors as locked and refusing to erase or program them.
Software command locking would probably involve implementing a few additional
commands.
I'm not sure what the others are.
Which locking method do you need?
--
Stephen Checkoway
Don't dynamically allocate the pflash's timer. But do use timer_del in
an unrealize function to make sure that the timer can't fire after the
pflash_t has been freed.
Signed-off-by: Stephen Checkoway
---
hw/block/pflash_cfi02.c | 15 +++
1 file changed, 11 insertions(
On Feb 19, 2019, at 01:09, Markus Armbruster wrote:
> Stephen Checkoway writes:
>
>> On Feb 18, 2019, at 13:08, Markus Armbruster wrote:
>>
>>> Any chance you could do multiple region support, too?
>>
>> Can you point me at the data sheet for a flas
On Feb 18, 2019, at 13:08, Markus Armbruster wrote:
> Stephen Checkoway writes:
>
>> On Feb 18, 2019, at 08:43, Thomas Huth wrote:
>>
>>> On 18/02/2019 07.07, Stephen Checkoway wrote:
>>>> Hi all,
>>>>
>>>> I'v
musicpal,accel=qtest "
>"-drive if=pflash,file=%s,format=raw", filename);
If I do that, will it be possible for the test to override the properties set
by pflash_cfi02_register? It looks like I should be able to use -global to set
properties that aren't set explicitly.
Thank you,
--
Stephen Checkoway
it wouldn't connect it to the sysbus).
Any suggestions would be appreciated.
Thank you,
--
Stephen Checkoway
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