Re: [PATCH v3 05/10] arm/cpu: accessors for writable id registers

\ +}) + s/sysreg/REG/ Also GET_IDREG_WRITABLE doesn't seem to be used in this series. Sebastian

Re: [PATCH v3 13/14] arm/cpu: Add sysreg generation scripts

idreg = 0 + } This doesn't seem to be used. I guess this is in preparation for later usage, when this can do more than just the plain register definition? Sebastian

Re: [PATCH v3 00/14] arm: rework id register storage

00755 scripts/update-aarch64-sysreg-code.sh create mode 100644 target/arm/cpu-sysregs.h create mode 100644 target/arm/cpu-sysregs.h.inc Reviewed-by: Sebastian Ott

Re: [PATCH v3 01/14] arm/cpu: Add sysreg definitions in cpu-sysregs.h

e extended when/if there's an actual need.. Sebastian

[PATCH v3 3/6] hw/riscv: Make FDT optional for MPFS

. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 56 +++--- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f477d2791e..844dc0545c 100644 --- a/hw/riscv/microchip_pfsoc.c

[PATCH v3 0/6] Improve Microchip Polarfire SoC customization

\ -kernel rtos.elf v2: * Add documentation update. * In patch 3, warn if no device tree is specified. * In patch 4, use riscv_find_firmware() to locate the firmware shipped with Qemu. v3: * In patch 4, add support for Qemu test runs. Sebastian Huber (6): hw/misc: Add MPFS system reset

[PATCH v3 1/6] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7

[PATCH v3 6/6] hw/riscv: microchip_pfsoc: Rework documentation

Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber --- docs/system/riscv/microchip-icicle-kit.rst | 124 +++-- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git

[PATCH v3 4/6] hw/riscv: Allow direct start of kernel for MPFS

d_firmware(). Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 59 +++--- 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 844dc0545c..5c9f7f643f 100644 --- a/hw/riscv/microch

[PATCH v3 2/6] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv

[PATCH v3 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 49

[PATCH] hw/riscv: Fix test for microchi-icicle-kit

out! ERROR:../hw/riscv/boot.c:164:riscv_load_firmware: \ assertion failed: (firmware_filename != NULL) Use an approach similar to riscv_find_and_load_firmware(). Reported-by: Daniel Henrique Barboza Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 12 +++- 1 file

[PATCH v2 6/6] hw/riscv: microchip_pfsoc: Rework documentation

Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber --- docs/system/riscv/microchip-icicle-kit.rst | 124 +++-- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git

[PATCH v2 4/6] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pf

[PATCH v2 3/6] hw/riscv: Make FDT optional for MPFS

. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 56 +++--- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f477d2791e..844dc0545c 100644 --- a/hw/riscv/microchip_pfsoc.c

[PATCH v2 2/6] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv

[PATCH v2 0/6] Improve Microchip Polarfire SoC customization

\ -kernel rtos.elf v2: * Add documentation update. * In patch 3, warn if no device tree is specified. * In patch 4, use riscv_find_firmware() to locate the firmware shipped with Qemu. Sebastian Huber (6): hw/misc: Add MPFS system reset support hw/riscv: More flexible FDT placement for

[PATCH v2 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 49

[PATCH v2 1/6] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7

Re: [PATCH 3/5] hw/riscv: Make FDT optional for MPFS

- Am 24. Feb 2025 um 6:22 schrieb Alistair Francis alistai...@gmail.com: > On Fri, Feb 14, 2025 at 4:27 PM Sebastian Huber > wrote: >> >> Real-time kernels such as RTEMS or Zephyr may use a static device tree >> built into the kernel image. Do not require t

Re: [PATCH 0/5] Improve Microchip Polarfire SoC customization

- Am 20. Feb 2025 um 23:29 schrieb Philippe Mathieu-Daudé phi...@linaro.org: > Hi Conor, > > On 20/2/25 19:30, Conor Dooley wrote: >> +cc qemu-riscv, Alistar. >> >> On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: >>> Booting the microchip

[PATCH v2] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- v2: Use riscv_find_fir

[PATCH 2/5] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index ec7e2e4226

[PATCH 5/5] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 49 +++--- include/hw/riscv

[PATCH 0/5] Improve Microchip Polarfire SoC customization

\ -kernel rtos.elf Sebastian Huber (5): hw/misc: Add MPFS system reset support hw/riscv: More flexible FDT placement for MPFS hw/riscv: Make FDT optional for MPFS hw/riscv: Allow direct start of kernel for MPFS hw/riscv: Configurable MPFS CLINT timebase freq hw/misc

[PATCH 1/5] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7

[PATCH 4/5] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pf

[PATCH 3/5] hw/riscv: Make FDT optional for MPFS

Real-time kernels such as RTEMS or Zephyr may use a static device tree built into the kernel image. Do not require to use the -dtb option if -kernel is used for the microchip-icicle-kit machine. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 53

Re: [PATCH v2] pci: ensure valid link status bits for downstream ports

Hello Michael, Marcel, On Tue, 3 Dec 2024, Alex Williamson wrote: On Tue, 3 Dec 2024 13:19:28 +0100 Sebastian Ott wrote: PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport :08:01.0: pcie

Re: [PATCH v2] pci: ensure valid link status bits for downstream ports

Hi, On Tue, 3 Dec 2024, Alex Williamson wrote: On Tue, 3 Dec 2024 13:19:28 +0100 Sebastian Ott wrote: PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport :08:01.0: pciehp: Slot(2): Ca

Re: [PATCH RFCv2 00/20] kvm/arm: Introduce a customizable aarch64 KVM host model

M between 2 similar machines that only differ in the DIC bit of the cache type register using: -cpu host,SYSREG_CTR_EL0_DIC=0 This allows me to get rid of my horrid qemu hacks to achieve the same. Thanks, Sebastian

[PATCH v2] pci: ensure valid link status bits for downstream ports

e sure downstream ports always have a valid LNKSTA. Signed-off-by: Sebastian Ott Tested-by: Zhenyu Zhang --- hw/pci/pcie.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 0b455c8654..1b12db6fa2 100644 --- a/hw/pci/pcie.c +

Re: [PATCH] pci: ensure valid link status bits for downstream ports

On Mon, 11 Nov 2024, Sebastian Ott wrote: PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport :08:01.0: pciehp: Slot(2): Card present pcieport :08:01.0: pciehp: Slot(2): Link Up pcieport 00

Re: [PATCH] pci: ensure valid link status bits for downstream ports

On Mon, 11 Nov 2024, Sebastian Ott wrote: PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport :08:01.0: pciehp: Slot(2): Card present pcieport :08:01.0: pciehp: Slot(2): Link Up pcieport 00

[PATCH] pci: ensure valid link status bits for downstream ports

nk: status 0x2000 There's 2 cases where LNKSTA isn't setup properly: * the downstream device has no express capability * max link width of the bridge is 0 Fix these by making the LNKSTA modifications independent of each other. Signed-off-by: Sebastian Ott ---

Re: [PATCH 1/2] hw/arm/boot: Use hooks if PSCI is disabled

- Am 30. Sep 2024 um 17:16 schrieb Peter Maydell peter.mayd...@linaro.org: > On Mon, 23 Sept 2024 at 04:57, Sebastian Huber > wrote: >> >> In arm_load_kernel(), use the secondary boot hooks provided by the >> platform if PSCI is disabled also while booting a no

[PATCH 1/2] hw/arm/boot: Use hooks if PSCI is disabled

resetting a non-Linux kernel. This change allows a more accurate simulation of the platform reset behaviour. Signed-off-by: Sebastian Huber --- hw/arm/boot.c | 30 +++--- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index

[PATCH 2/2] hw/arm/xilinx_zynq: Add CPU1 reset

After a system reset (SRST), the CPU1 should execute a wfe instruction and then load the start address from 0xfff0: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 25 + 1 file

[PATCH 0/2] Fix secondary CPU reset for Xilinx Zynq 7000

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 Sebastian Huber (2): hw/arm/boot: Use hooks if PSCI is disabled hw/arm/xilinx_zynq: Add CPU1 reset hw/arm/boot.c| 30 +++--- hw/arm/xilinx_zynq.c | 25 + 2 files change

Re: Xilinx Zynq 7000 Start of CPU1

- Am 18. Sep 2024 um 11:13 schrieb Sebastian Huber sebastian.hu...@embedded-brains.de: > Hello, > > I recently added the support for CPU1 to the xilinx-zynq-a9 machine > (hw/arm/xilinx_zynq.c). However, the reset behaviour doesn't match exactly > with > the hardwar

Xilinx Zynq 7000 Start of CPU1

0: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 It would be great if someone has a hint for me how I can add this startup code for CPU1 at address region 0xFE00 to 0xFFF0. Kind regards, Sebastian -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dorn

Are floating-point exceptions usable on AArch64?

ouble x = 0x0; volatile double y = 0x0; x /= y; When I look with the debugger at $fpcr it still says 0x0 after the msr. Are floating-point exceptions usable on AArch64 in general? -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebas

Re: [PATCH] hw/arm/xilinx_zynq: Enable Security Extensions

Hello Peter, - Am 29. Aug 2024 um 14:50 schrieb Peter Maydell peter.mayd...@linaro.org: > On Wed, 28 Aug 2024 at 01:51, Sebastian Huber > wrote: >> >> The system supports the Security Extensions (core and GIC). This change is >> necessary to run tests which p

[PATCH] hw/arm/xilinx_zynq: Enable Security Extensions

The system supports the Security Extensions (core and GIC). This change is necessary to run tests which pass on the real hardware. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 8 1 file changed, 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c

[PATCH] hw/arm/xilinx_zynq: Fix IRQ/FIQ routing

Fix the system bus interrupt line to CPU core assignment. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fb..c79661bbc1 100644 --- a/hw/arm/xilinx_zynq.c

Re: [PATCH v2 0/2] Zynq 7000 Improvements

On 30.05.24 12:30, Peter Maydell wrote: On Fri, 24 May 2024 at 13:08, Sebastian Huber wrote: v2: * Add Kconfig support * Add array of CPUs to ZynqMachineState * Add FIQ support Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU

[PATCH v2 1/2] hw/arm/xilinx_zynq: Add cache controller

The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber --- hw/arm/Kconfig | 1 + hw/arm/xilinx_zynq.c | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm

[PATCH v2 0/2] Zynq 7000 Improvements

v2: * Add Kconfig support * Add array of CPUs to ZynqMachineState * Add FIQ support Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU cores hw/arm/Kconfig | 1 + hw/arm/xilinx_zynq.c | 55

[PATCH v2 2/2] hw/arm/xilinx_zynq: Support up to two CPU cores

The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 54 +++- 1 file changed, 33 insertions(+), 21 deletions(-) diff

Re: [PATCH 2/2] hw/arm/xilinx_zynq: Support up to two CPU cores

Hello Peter, thanks for the review. On 20.05.24 15:58, Peter Maydell wrote: On Tue, 7 May 2024 at 14:04, Sebastian Huber wrote: The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian

[PATCH v2 1/2] hw/intc/arm_gic: Fix set pending of PPIs

According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Seba

[PATCH v2 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn

rupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 7 +++ 1 file changed, 7 inserti

[PATCH v2 0/2] Fix GICv2 handling of pending interrupts

v2: * Fix handling of SPIs. * Remove pending state if not in new target list. Sebastian Huber (2): hw/intc/arm_gic: Fix set pending of PPIs hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn hw/intc/arm_gic.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.35.3

Re: [PATCH 0/2] Zynq 7000 SoC improvements

Hello, is the mailing list the right place for contributions like this? On 07.05.24 15:03, Sebastian Huber wrote: Add support for the cache controller and up to two Cortex-A9 MPCore. Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU

[PATCH 1/2] hw/arm/xilinx_zynq: Add cache controller

The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index

[PATCH 2/2] hw/arm/xilinx_zynq: Support up to two CPU cores

The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian Huber --- hw/arm/xilinx_zynq.c | 42 +++--- 1 file changed, 27 insertions(+), 15 deletions(-) diff

[PATCH 0/2] Zynq 7000 SoC improvements

Add support for the cache controller and up to two Cortex-A9 MPCore. Sebastian Huber (2): hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU cores hw/arm/xilinx_zynq.c | 43 --- 1 file changed, 28 insertions(+), 15

[PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs

According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Seba

[PATCH 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn

rupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 7 +++ 1 file changed, 7 inserti

[PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs

According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Seba

[PATCH 2/2] hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn

rupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 7 +++ 1 file changed, 7 inserti

Re: [PATCH 2/2] virtio-gpu: fix scanout migration post-load

On Wed, 17 Jan 2024, Marc-André Lureau wrote: On Tue, Jan 16, 2024 at 3:17 PM Sebastian Ott wrote: On Mon, 15 Jan 2024, marcandre.lur...@redhat.com wrote: +scanout->ds = qemu_create_displaysurface_pixman(res->image); +if (!scanout->ds) { +retur

Re: [PATCH v5] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

until the vcpu PMU is initialized). Sebastian

Re: [PATCH v5] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

1752000 seconds user 0.0 seconds sys As we can see, the cycle counter has been disabled in the guest, but other pmu events are still work. Signed-off-by: Shaoqin Huang Reviewed-by: Sebastian Ott

Re: [PATCH 2/2] virtio-gpu: fix scanout migration post-load

On Mon, 15 Jan 2024, marcandre.lur...@redhat.com wrote: +scanout->ds = qemu_create_displaysurface_pixman(res->image); +if (!scanout->ds) { +return -EINVAL; +} "qemu_create_displaysurface_pixman() never returns NULL." ;-)

Re: [PATCH v4] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

On Fri, 15 Dec 2023, Sebastian Ott wrote: On Thu, 14 Dec 2023, Eric Auger wrote: On 12/7/23 11:36, Shaoqin Huang wrote: +if (kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr)) { +warn_report("The kernel doesn't support the PMU Event Filter!\n"

Re: [PATCH v4] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

a VCPU, or to change the semantics of existing events. Sebastian

Re: [PATCH v3] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

if (pmu_filter_init) return; pmu_filter_init = true; which could also move above the other tests. Sebastian

Re: hanging process with commit 69562648f9 ("vl: revert behaviour for -display none")

On Mon, 27 Nov 2023, Peter Maydell wrote: On Mon, 27 Nov 2023 at 12:29, Sebastian Ott wrote: qemu fails to start a guest using the following command (the process just hangs): qemu-system-aarch64 -machine virt -cpu host -smp 4 -m 8192 -kernel /boot/vmlinuz-6.7.0-rc1 -initrd ~/basic.img -append

hanging process with commit 69562648f9 ("vl: revert behaviour for -display none")

splay none ..which I've used to debug a potential virtio-gpu issue. Bisect points to 69562648f9 ("vl: revert behaviour for -display none") Is that qemu cmd just invalid and shouldn't have worked in the first place? Sebastian

Re: [PATCH v1] arm/kvm: Enable support for KVM_ARM_VCPU_PMU_V3_FILTER

->has_pmu) { return; } +if (!pmu_filter_init) { +kvm_arm_pmu_filter_init(cs); +pmu_filter_init = true; pmu_filter_init could move inside kvm_arm_pmu_filter_init() - maybe together with a comment that this only needs to be called for 1 vcpu. Thanks, Sebastian

[PATCH] risu: Add test summary

dd that message when printing the trace to stdout (`-t -`). Tested: a) master/apprentice mode b) trace mode to file c) trace mode to stdout Suggested-by: Thomas Huth Signed-off-by: Sebastian Mitterle --- risu.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/

[PATCH] hw/arm: fix PMU IRQ registration

_IRQ to be a INTID but missed a case where the PMU IRQ is actually referred by its PPI index. Fix that by using INTID_TO_PPI() in that case. Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") Signed-off-by: Sebastian Ott --- hw/arm/virt.c | 3 ++- 1 file changed, 2 inser

[PATCH] hw/pci-bridge: make building pcie-to-pci bridge configurable

Introduce a CONFIG option to build the pcie-to-pci bridge. No functional change since it's enabled per default for PCIE_PORT=y. Signed-off-by: Sebastian Ott --- hw/pci-bridge/Kconfig | 5 + hw/pci-bridge/meson.build | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff

[PATCH v3] docs/s390x/pcidevices: document pci devices on s390x

Add some documentation about the zpci device and how to use it with pci devices on s390x. Used source: Cornelia Huck's blog post https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html Signed-off-by: Sebastian Mitterle Reviewed-by: C??dric Le Goater --- v3: add info zp

Re: [PATCH v2] docs/s390x/pcidevices: document pci devices on s390x

On Fri, Jan 27, 2023 at 11:30 AM Cornelia Huck wrote: > > On Fri, Jan 27 2023, Sebastian Mitterle wrote: > > > Add some documentation about the zpci device and how > > to use it with pci devices on s390x. > > > > Used source: Cornelia Huck's blog post >

Re: [PATCH v2] docs/s390x/pcidevices: document pci devices on s390x

On Fri, Jan 27, 2023 at 10:24 AM Thomas Huth wrote: > > On 27/01/2023 09.46, Sebastian Mitterle wrote: > > Add some documentation about the zpci device and how > > to use it with pci devices on s390x. > > Thanks for tackling this! ... some comments below... > > >

[PATCH v2] docs/s390x/pcidevices: document pci devices on s390x

Add some documentation about the zpci device and how to use it with pci devices on s390x. Used source: Cornelia Huck's blog post https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html Signed-off-by: Sebastian Mitterle --- v2: move section below 'Device support' -

[PATCH] docs/s390x/pcidevices: document pci devices on s390x

Add some documentation about the zpci device and how to use it with pci devices on s390x. Used source: Cornelia Huck's blog post https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html Signed-off-by: Sebastian Mitterle --- docs/system/s390x/pcidevices.rst

[PATCH] qemu-edid: Restrict input parameter -d to avoid division by zero

A zero value for dpi will lead to a division by zero in qemu_edid_dpi_to_mm(). Tested by runnig qemu-edid -dX, X = 0, 100. Resolves: qemu-project/qemu#1249 Suggested-by: Thomas Huth Signed-off-by: Sebastian Mitterle --- qemu-edid.c | 4 1 file changed, 4 insertions(+) diff --git a/qemu

[PATCH v2] virtiofsd: Do not support blocking flock

With the current implementation, blocking flock can lead to deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts to perform a blocking flock request. Signed-off-by: Sebastian Hasler --- tools/virtiofsd/passthrough_ll.c | 9 + 1 file changed, 9 insertions(+) diff --

Re: [PATCH] virtiofsd: Do not support blocking flock

On 11/01/2022 19:10, Sebastian Hasler wrote: With the current implementation, blocking flock can lead to deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts to perform a blocking flock request. Signed-off-by: Sebastian Hasler --- tools/virtiofsd/passthrough_ll.

[PATCH] virtiofsd: Do not support blocking flock

With the current implementation, blocking flock can lead to deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts to perform a blocking flock request. Signed-off-by: Sebastian Hasler --- tools/virtiofsd/passthrough_ll.c | 6 ++ 1 file changed, 6 insertions(+) diff --

[Bug 1749393] Re: sbrk() not working under qemu-user with a PIE-compiled binary?

I'm running qemu-arm version 4.2.1 (Debian 1:4.2-3ubuntu6.17) on Ubuntu 20.04.03, but I seem to still be affected by this (or something very much like it). In my case it is armhf exim4 crashing while creating a chroot on an amd64 host. The final command run from deeply within exim4's postinst is:

Re: [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI

Hello Luc, thanks for having a look at the patch. On 25/07/2021 10:08, Luc Michel wrote: Hi Sebastian, On 11:49 Fri 09 Jul , Sebastian Huber wrote: According to the GICv3 specification register GICD_ISPENDR0 is Banked for each You're referring to GICv3 but actually modifying GICv2

Re: [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI

On 09/07/2021 11:49, Sebastian Huber wrote: According to the GICv3 specification register GICD_ISPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case since GIC_NCPU == 8. For SPI, make the interrupt pending on all CPUs and not just

[PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI

is at least present on the i.MX7D which uses an Cortex-A7MPCore. Signed-off-by: Sebastian Huber --- hw/intc/arm_gic.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a994b1f024..8e377bac59 100644 --- a/hw/intc/arm_gi

[Bug 1799792] Re: Broken scaling with gtk,gl=on on a hidpi display

Still happening in QEMU 5.1.0 ** Changed in: qemu Status: Incomplete => New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1799792 Title: Broken scaling with gtk,gl=on on a hidpi display St

[Bug 1277433] Re: GDB context is inconsistent after "monitor system_reset"

With this Qemu: qemu-system-arm --version QEMU emulator version 4.2.50 (v4.2.0-1276-g863d2ed582) Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers I still have the same issue: (gdb) info registers r0 0x0 0 r1 0x9010001 15106

[Bug 1277433] Re: GDB context is inconsistent after "monitor system_reset"

I can also build the latest Git master of Qemu if this helps. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1277433 Title: GDB context is inconsistent after "monitor system_reset" Status in QEMU:

Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR

On 2019-09-26 13:06:34 [+0200], Paolo Bonzini wrote: > On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store > > Bypass Disable */ > > > > +#define CPUD_800_008_EBX_CLZERO

[PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR

The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform and could be passed to the guest. Signed-off-by: Sebastian Andrzej Siewior --- I tweaked the kernel to expose these flags and figured out that this is also missing in order see those bits in the guest. target/i386/

[Qemu-devel] Translation of qemu to Swedish...

Hi! I noticed that a translation to Swedish was missing, so I'd like to contribute that. Let me know if there is some issue and I'll do my best to fix it. :) / Sebastian >From 9d8525b987e0db8309b6221a7e2a292fa5db9eec Mon Sep 17 00:00:00 2001 From: Sebastian Rasmussen Date: Fri, 1

[Qemu-devel] Use Case for Qemu BT

So...this is not really a use-case per-say as it is actually a thing I would like to do but can't at present... Win 10 is lacking an ad2p sink and this means if I'm using it to play a windows-only game and want to stream from e.g. my phone to my computer, I can't (natively). Enter Linux, which mos

[Qemu-devel] [Bug 1821515] Re: qemu-ppc (user) incorrectly converts float(nan)->double(non-nan)

We also hit this regression when testing CompCert for e5500 with qemu 3.1.0. The minimal example > #include > #include > > union C { float f; unsigned long l; }; > int main (void) { > union C c; > c.f = NAN; > printf("Float: %f\n Hex: 0x%x\n", c.f, c.l); > printf("The above fl

[Qemu-devel] [Bug 1799792] [NEW] Broken scaling with gtk, gl=on on a hidpi display

Public bug reported: Tested on QEMU 3.0.0 on Arch Linux. I'm using a hidpi screen, and therefore use those environment variables in order to have GTK+ apps properly scaled: GDK_SCALE=2 GDK_DPI_SCALE=0.5 However, QEMU, when launched with "-display gtk,gl=on" option, doesn't scale the window cont

[Qemu-devel] [PATCH] SDL: set a hint to not bypass the window compositor

Without that, window effects in KWin get suspended as soon as any qemu-sdl window becomes visible. While the SDL default makes sense for games, it's not really suitable for QEMU. Signed-off-by: Sebastian Krzyszkowiak --- ui/sdl2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ui/s

Re: [Qemu-devel] [PATCH] i386: correct cpu_x86_cpuid(0xd)

On 2018-10-17 20:40:17 [+0200], Paolo Bonzini wrote: > It's queued for my next pull request. thanks. > Paolo Sebastian

Re: [Qemu-devel] [PATCH] i386: correct cpu_x86_cpuid(0xd)

On 2018-09-28 11:54:11 [-0300], Eduardo Habkost wrote: > On Fri, Sep 28, 2018 at 12:43:19PM +0200, Sebastian Andrzej Siewior wrote: > > Intel SDM says for CPUID function 0DH, sub-function 0: > > > > | • ECX enumerates the size (in bytes) required by the XSAVE instruction >

[Qemu-devel] [PATCH] i386: correct cpu_x86_cpuid(0xd)

for an | XSAVE area containing all the user state components corresponding to bits | currently set in XCR0. Signed-off-by: Sebastian Andrzej Siewior --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

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