Philippe Mathieu-Daudé writes:
> When instanciating the machine model, the machine_init()
> implementations usually create the CPUs, so have access
> to its first CPU. Use that rather then the &first_cpu
> global.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Samuel Tardieu
ners file: from now on,
> Samuel Tardieu who is behind the project will be taking up the role of
> maintainer.
>
> This commit updates maintainers and the list of files, and places the
> two devices in alphabetical order.
>
> Signed-off-by: Inès Varhol
Signed-off-by: Samuel Tardieu
Felipe Balbi writes:
> +qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
Hi Felipe.
This should be 2, not 4. From RM0454 section 11.1 on page 250: "4 programmable
priority levels (2 bits of interrupt priority are used)".
Sam
--
Samuel Tardieu
jump.c:11:3: warning: ‘foo’ may be used uninitialized
[-Wmaybe-uninitialized]
11 | free(foo);
| ^
jump.c:8:9: note: ‘foo’ was declared here
8 | char *foo = malloc(30);
| ^~~
Best.
Sam
--
Samuel Tardieu
stay in their original positions. I even opened
an issue on b4 a few weeks ago because of this
<https://github.com/mricon/b4/issues/16>, and I reverted to using
git-publish. But if this is ok to use an arbitrary order for
non-S-o-b headers, I can get back to b4.
Sam
--
Samuel Tardieu
Arnaud Minier writes:
+ * The procedure is taken from a program by Samuel Tardieu.
You may drop this line as I used the same procedure which is used
in other tests, this does not deserve a mention here.
Sam
--
Samuel Tardieu
Signed-off-by: Samuel Tardieu
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
---
hw/timer/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 3eccef83858..8145e18e3da 100644
--- a/hw/timer/tr
Samuel Tardieu writes:
The shix machine was a research project started around 2003 at
Télécom Paris. Preliminary support in QEMU was added in 2005
back when the QEMU architecture was less structured than it is
now. Unfortunately, the support for the shix machine and its
peripherals, such as
The 16MiB flash device is only used by the deprecated shix machine.
Its code it old and unmaintained, and has never been adapted to the
QOM architecture. It still contains debug statements and uses global
variables. It is time to deprecate it.
Signed-off-by: Samuel Tardieu
Reviewed-by: Cédric Le
The shix machine has been designed and used at Télécom Paris from 2003
to 2010. It had been added to QEMU in 2005 and has not been maintained
since. Since nobody is using the physical board anymore nor interested
in maintaining the QEMU port, it is time to deprecate it.
Signed-off-by: Samuel
QOM model and still
contains debug fprintf statements.
Samuel Tardieu (2):
target/sh4: Deprecate the shix machine
hw/block: Deprecate the TC58128 block device
docs/about/deprecated.rst | 5 +
hw/block/tc58128.c| 1 +
hw/sh4/shix.c | 1 +
3 files changed, 7 insertions
ned"?
You're right. I removed the extra part in both the shix and the
tc58128 deprecation messages.
Sam
--
Samuel Tardieu
The 16MiB flash device is only used by the deprecated shix machine.
Its code it old and unmaintained, and has never been adapted to the
QOM architecture. It still contains debug statements and uses global
variables. It is time to deprecate it.
Signed-off-by: Samuel Tardieu
---
docs/about
The shix machine has been designed and used at Télécom Paris from 2003
to 2010. It had been added to QEMU in 2005 and has not been maintained
since. Since nobody is using the physical board anymore nor interested
in maintaining the QEMU port, it is time to deprecate it.
Signed-off-by: Samuel
QOM model and still
contains debug fprintf statements.
Samuel Tardieu (2):
target/sh4: Deprecate the shix machine
hw/block: Deprecate the TC58128 block device
docs/about/deprecated.rst | 5 +
hw/block/tc58128.c| 1 +
hw/sh4/shix.c | 1 +
3 files changed, 7 insertions
A SoC will not have a direct access to the NVIC embedded in its ARM
core. By aliasing the "num-prio-bits" property similarly to what is
done for the "num-irq" one, a SoC can easily configure it on its
armv7m instance.
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
e). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.
Signed-off-by: Samuel Tardieu
Suggested-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
Reviewed-by: Peter Maydell
---
hw/intc/armv7m_n
the Based-on: trailer
in the cover letter.
- Fix a typo in one of the commit messages ("compatibility")
Based-on: <20240106163905.42027-1-ines.var...@telecom-paris.fr>
([PATCH v5 0/2] Add minimal support for the B-L475E-IOT01A board)
Samuel Tardieu (3):
hw/intc/armv7m_nvic: ad
Update the number of priority bits for a number of existing
SoCs according to their technical documentation:
- STM32F100/F205/F405/L4x5: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
---
hw/arm/stellaris.c | 2 ++
hw/arm
An apparent copy-paste error tests for the presence of the
virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw
device.
Signed-off-by: Samuel Tardieu
---
tests/qtest/virtio-ccw-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/virtio-ccw
ange after Inès has submitted an updated version of
her "Add minimal support for the B-L475E-IOT01A board" serie on
which this one is based.
Best.
Sam
--
Samuel Tardieu
On 04/01/2024 14:40, Philippe Mathieu-Daudé wrote:
On 4/1/24 14:23, Samuel Tardieu wrote:
Philippe Mathieu-Daudé writes:
This doesn't build:
../../hw/misc/stm32l4x5_exti.c:172:9: error: expected expression
const uint32_t set1 = value & ~DIRECT_LINE_MASK1;
[…]
I could bu
mpiler or option do you use for
checking? I have no problem building this using "./configure
--target-list=arm-softmmu" with GCC 12.3.0.
Sam
--
Samuel Tardieu
Télécom Paris - Institut Polytechnique de Paris
If "busses" might be encountered as a plural of "bus" (5 instances),
the correct spelling is "buses" (26 instances). Fixing those 5
instances makes the doc more consistent.
Signed-off-by: Samuel Tardieu
---
docs/system/arm/palm.rst| 2 +-
docs/system/arm/x
guest-exec invocation does not need the full path of the executable to
execute. Using only the command names ensures correct execution of the
test on systems not adhering to the FHS.
Signed-off-by: Samuel Tardieu
---
tests/unit/test-qga.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
e). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.
Signed-off-by: Samuel Tardieu
Suggested-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
---
hw/intc/armv7m_nvic.c | 23 +
A SoC will not have a direct access to the NVIC embedded in its ARM
core. By aliasing the "num-prio-bits" property similarly to what is
done for the "num-irq" one, a SoC can easily configure it on its
armv7m instance.
Signed-off-by: Samuel Tardieu
---
hw/arm/armv7m.c | 2 +
Update the number of priority bits for a number of existing
SoCs according to their technical documentation:
- STM32F100/F205/F405/L4x5: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
---
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm
("compatibility")
Based-on: <20231221213838.54944-1-ines.var...@telecom-paris.fr>
([PATCH v4 0/2] Add minimal support for the B-L475E-IOT01A board)
Samuel Tardieu (3):
hw/intc/armv7m_nvic: add "num-prio-bits" property
hw/arm/armv7m: alias the NVIC "num-prio-bits&quo
stall directory:
/data/dictionary.txt
This works correctly on my NixOS system using a non-FHS layout and
properly locates the codespell file.
This patch made me find a typo in one of my commit messages.
Tested-by: Samuel Tardieu
Sam
--
Samuel Tardieu
Télécom Paris - Institut Polytechnique de Paris
ain "env", such as
"/usr/bin/env application" works. This is the case for example on
NixOS, which is more and more used in research environments for
their easily reproducible build environments.
Sam
--
Samuel Tardieu
Télécom Paris - Institut Polytechnique de Paris
the
"Based-on:" tag so that patchew gets it right?
Anyway, I just wanted to say that this patchset is on my
todo list to review but I'm not going to be able to get to
it before I break for Christmas, so I'll get back to it
in January. Thanks for the contribution!
Noted!
Best.
Sam
--
Samuel Tardieu
By calling `error_setg_errno()` before jumping to the cleanup-on-error
path at the `fail` label, the cleanup path is clearer.
Signed-off-by: Samuel Tardieu
---
tcg/region.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index 467e51cf6f
preserves the fall-through
case while avoiding testing an always false condition.
Changes from v1:
- Add a comment explaining that `buf_rx` does not require cleanup
- Use a unique cleanup path for the function by setting `errno` before
jumping to the cleanup block.
Samuel Tardieu (2):
tcg: Remove
The `fail_rx`/`fail` block is only entered while `buf_rx` is equal to
its initial value `MAP_FAILED`. The `munmap(buf_rx, size);` was never
executed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2030
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
---
tcg/region.c | 4
r jump to `fail`
- calling `error_setg_errno()` at the right place before jumping
to `fail`
I will produce a v2 to make this proposal clearer.
Sam
--
Samuel Tardieu
Samuel Tardieu (3):
hw/intc/armv7m_nvic: add "num-prio-bits" property
hw/arm/armv7m: alias the NVIC "num-prio-bits" property
hw/arm/socs: configure priority bits for existing SOCs
Any idea to why patchew fails to apply thoses patches? The mbox at
<h
Update the number of priority bits for a number of existing
SOCsaccording to their technical documentation:
- STM32F100/F205/F405: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
---
hw/arm/stellaris.c | 2 ++
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c
to preserve
backward compatibility.
Based-on: <20220813112559.1974427-1-anton.koch...@proton.me>
([PATCH] hw/arm/nvic: implement "num-prio-bits" property)
Samuel Tardieu (3):
hw/intc/armv7m_nvic: add "num-prio-bits" property
hw/arm/armv7m: alias the NVIC "num-pr
e). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibiltiy.
Signed-off-by: Samuel Tardieu
Suggested-by: Anton Kochkov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
---
hw/intc/armv7m_nvic.c | 23 +
Signed-off-by: Samuel Tardieu
---
hw/arm/armv7m.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index d10abb36a8..4fda2d1d47 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -256,6 +256,8 @@ static void armv7m_instance_init(Object *obj
`buf_rw` is always `NULL` when jumping to the `fail` label. Move the
label `down` after the `if (buf_rw) { ... }` statement.
Signed-off-by: Samuel Tardieu
---
tcg/region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/region.c b/tcg/region.c
index 6d657e8c33
The `fail_rx`/`fail` block is only entered while `buf_rx` is equal to
its initial value `MAP_FAILED`. The `munmap(buf_rx, size);` was never
executed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2030
Signed-off-by: Samuel Tardieu
---
tcg/region.c | 3 ---
1 file changed, 3 deletions
preserves the fall-through
case while avoiding testing an always false condition.
Samuel Tardieu (2):
tcg: Remove unreachable code
tcg: Jump after always false condition
tcg/region.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
--
2.42.0
Signed-off-by: Samuel Tardieu
---
docs/tools/qemu-img.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/tools/qemu-img.rst b/docs/tools/qemu-img.rst
index 4459c065f1..3653adb963 100644
--- a/docs/tools/qemu-img.rst
+++ b/docs/tools/qemu-img.rst
@@ -406,7 +406,7
uld be the same as
today without the patch.
Other problem is the __tune_i386__ is also set when -mtune=i386
(but with -march=i686).
Indeed, this is the case for GCC (not clang).
Sam
--
Samuel Tardieu
Télécom Paris - Institut Polytechnique de Paris
h GCC and LLVM when using -march=i386.
Sam
--
Samuel Tardieu
Télécom Paris - Institut Polytechnique de Paris
This file is the only one involved in the compilation process which
still uses the /bin/bash path.
Signed-off-by: Samuel Tardieu
---
target/hexagon/idef-parser/prepare | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/idef-parser/prepare
b/target/hexagon/idef
nic -net tap" and that's it, the qemu instance
has access to my local network, DHCP server, IPv6 routers, etc.
Sam
--
Samuel Tardieu -- [EMAIL PROTECTED] -- http://www.rfc1149.net/
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on it while I am away, drop me a mail in the
next 48 hours so that I can send you the patch.
I plan to end this port when I come back in January 2006.
Sam
--
Samuel Tardieu -- [EMAIL PROTECTED] -- http://www.rfc1149.net/
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