[PATCH v2 0/2] Emulated AMD IOMMU cleanup and fixes

base address from the IVRS table and not the one provided by PCI capability. Sairaj Kodilkar (2): amd_iommu: Use correct DTE field for interrupt passthrough amd_iommu: Use correct bitmask to set capability BAR hw/i386/amd_iommu.c | 10 +- hw/i386/amd_iommu.h | 2 +- 2

[PATCH 2/2] amd_iommu: Use correct bitmask to set capability BAR

AMD IOMMU provides the base address of control registers through IVRS table and PCI capability. Since this base address is of 64 bit, use 32 bits mask (instead of 16 bits) to set BAR low and high. Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Sairaj Kodilkar R

[PATCH 1/2] amd_iommu: Use correct DTE field for interrupt passthrough

Interrupt passthrough is determine by the bits 191,190,187-184. These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence replace dte[3] by dte[2]. Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled") Signed-off-by: Sairaj Kodilkar R

[PATCH] amd_iommu: Fix kvm_enable_x2apic link error with clang in non-KVM builds

mmu: Check APIC ID > 255 for XTSup) Signed-off-by: Sairaj Kodilkar Signed-off-by: Santosh Shukla Tested-by: Phil Dennis-Jordan --- hw/i386/amd_iommu.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 13af7211e11d..af0f4d