[PATCH] target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry

this bit use the convenience pmp_is_locked() function rather than directly checking PMP_LOCK since this function checks mseccfg.RLB. Signed-off-by: Rob Bradford --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index

[PATCH] target/riscv: Fix minor whitespace issue in riscv_cpu_properties

The mvendorid/mimpid/marchid properties have the wrong amount of whitespace ahead of them. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2..cca24b9f1f 100644

[PATCH 0/2] disas/riscv: Add missing Sdtrig CSRs

Add missing Sdtrig CSRs per the latest RISC-V Debug specification. (+ minor whitespace fix) Rob Bradford (2): disas/riscv: Fix minor whitespace issues disas/riscv: Add missing Sdtrig CSRs disas/riscv.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.48.1

[PATCH 1/2] disas/riscv: Fix minor whitespace issues

Some extra spaces made into into the RISC-V opcode data table. Signed-off-by: Rob Bradford --- disas/riscv.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 4075ed6bfe..305dd40ac4 100644 --- a/disas/riscv.c +++ b/disas/riscv.c

[PATCH 2/2] disas/riscv: Add missing Sdtrig CSRs

This reflects the latest frozen version of the RISC-V Debug specification (1.0.0-rc4) which includes the Sdtrig extension. Signed-off-by: Rob Bradford --- disas/riscv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 305dd40ac4

[PATCH] target/riscv: Set vtype.vill on CPU reset

l on reset. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4bda754b01..af602e3caf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(O

[PATCH v2] disas/riscv: Add decode for Zawrs extension

From: Balaji Ravikumar Add disassembly support for these instructions from Zawrs: * wrs.sto * wrs.nto Signed-off-by: Balaji Ravikumar Signed-off-by: Rob Bradford --- disas/riscv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 05b663ebfe

[PATCH] disas/riscv: Add decode for Zawrs extension

From: Balaji Ravikumar Add disassembly support for these instructions from Zawrs: * wrs.sto * wrs.nto Signed-off-by: Balaji Ravikumar Signed-off-by: Rob Bradford --- disas/riscv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 90d6b26de9

[PATCH v2] target/riscv: Remove experimental prefix from "B" extension

This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Since this is now a ratified extension add it to the list of extensions included in the "max" CPU variant. Signed-off-by: Rob Bradford Reviewed-by: Andrew Jone

[PATCH] target/riscv: Remove experimental prefix from "B" extension

This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v3 3/3] target/riscv: Expose Zaamo and Zalrsc extensions

Expose the newly added extensions to the guest and allow their control through the CPU properties. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8d3ec74a1c..604baf53c8 100644 --- a/target

[PATCH v3 2/3] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 56 +++-- 1 file changed, 34 inserti

[PATCH v3 1/3] target/riscv: Add Zaamo and Zalrsc extension infrastructure

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_cfg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv

[PATCH v3 0/3] target/riscv: Add support for Zaamo & Zalrsc

thub.com/riscv/riscv-zaamo-zalrsc Changes since V2: - Split extension exposure from infrastructure (Alistair) Changes since V1: - Fix commit message that did not account for earlier fix (Daniel) Rob Bradford (3): target/riscv: Add Zaamo and Zalrsc extension infrastructure target/riscv:

[PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 + target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 7 insertions

[PATCH v2 0/2] target/riscv: Add support for Zaamo & Zalrsc

thub.com/riscv/riscv-zaamo-zalrsc Changes since V1: - Fix commit message that did not account for earlier fix (Daniel) Rob Bradford (2): target/riscv: Add Zaamo and Zalrsc extensions target/riscv: Check 'A' and split extensions for atomic instructions target/riscv/cpu.c

[PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 56 +++-- 1 file changed, 34 inserti

Re: [PATCH 2/2] target/riscv: Check 'A' and split extensions for atomic instructions

On Thu, 2024-01-18 at 16:49 -0300, Daniel Henrique Barboza wrote: > > > On 1/15/24 13:25, Rob Bradford wrote: > > Following the pattern for 'M' and Zmmul check if either the 'A' > > extension is enabled or the appropriate split extension for the

[PATCH 2/2] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Also remove the assumption that only checking for 64-bit systems is required for the double word variants. Signed-off-by: Rob Bradfor

[PATCH 1/2] target/riscv: Add Zaamo and Zalrsc extensions

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 + target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b

[PATCH 0/2] target/riscv: Add support for Zaamo & Zalrsc

thub.com/riscv/riscv-zaamo-zalrsc Rob Bradford (2): target/riscv: Add Zaamo and Zalrsc extensions target/riscv: Check 'A' and split extensions for atomic instructions target/riscv/cpu.c | 5 +++ target/riscv/cpu_cfg.h | 2 + target/riscv/i

Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

On Fri, 2024-01-12 at 17:08 +0100, Andrew Jones wrote: > On Thu, Jan 11, 2024 at 03:17:25PM +0000, Rob Bradford wrote: > > + Ved > > > > On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote: > > > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote: > &g

Re: [PATCH 0/2] Export debug triggers as an extension

On Fri, 2024-01-12 at 13:52 +1000, Alistair Francis wrote: > On Thu, Jan 11, 2024 at 5:20 AM Daniel Henrique Barboza > wrote: > > > > Himanshu, > > > > We spoke offline but let's make everyone aware: > > > > - 'sdtrig' should be marked with 'x-' and be an experimental > > extension since > > th

[PATCH v2 1/2] target/riscv: Add infrastructure for 'B' MISA extension

Add the infrastructure for the 'B' extension which is the union of the Zba, Zbb and Zbs instructions. Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + target/ris

[PATCH v2 0/2] target/riscv: Add support for 'B' extension

variant as misa.B is reserved until spec is at least frozen (Daniel & Drew) Rob Bradford (2): target/riscv: Add infrastructure for 'B' MISA extension target/riscv: Add step to validate 'B' extension target/riscv/cpu.c | 5 +++-- target/riscv

[PATCH v2 2/2] target/riscv: Add step to validate 'B' extension

If the B extension is enabled warn if the user has disabled any of the required extensions that are part of the 'B' extension. Conversely enable the extensions that make up the 'B' extension if it is enabled. Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza

Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type

On Thu, 2024-01-11 at 11:53 -0300, Daniel Henrique Barboza wrote: > > > On 1/11/24 10:02, Andrew Jones wrote: > > On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza > > wrote: > > > > > > > > > On 1/9/24 14:07, Rob Bra

Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

+ Ved On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote: > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote: > > On Tue, Jan 09, 2024 at 05:07:35PM +0000, Rob Bradford wrote: > > > Add the infrastructure for the 'B' extension which is the union > &g

[PATCH] target/riscv: Check for 'A' extension on all atomic instructions

Add requirement that 'A' is enabled for all atomic instructions that lack the check. This makes the 64-bit versions consistent with the 32-bit versions in the same file. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 11 +++ 1 file changed, 11

[PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

Add the infrastructure for the 'B' extension which is the union of the Zba, Zbb and Zbs instructions. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 1 + 3 files changed, 5 insertions(+), 2 deletion

[PATCH 2/3] target/riscv: Add step to validate 'B' extension

If the B extension is enabled warn if the user has disabled any of the required extensions that are part of the 'B' extension. Conversely enable the extensions that make up the 'B' extension if it is enabled. Signed-off-by: Rob Bradford --- target/risc

[PATCH 0/3] target/riscv: Add support for 'B' extension

o on in QEMU this extension is not enabled by default in any cpu other than the 'max' variant. Cheers, Rob [1] - https://github.com/riscv/riscv-b [2] - https://patchew.org/QEMU/20231218125334.37184-1-dbarb...@ventanamicro.com/20231218125334.37184-16-dbarb...@ventanamicro.com

[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type

Signed-off-by: Rob Bradford --- target/riscv/tcg/tcg-cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f10871d352..9705daec93 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -999,7

Re: [PATCH 1/2] target/riscv: Add support for Zacas extension

Hi Alistair, Thanks for providing some feedback - responses below: On Mon, 2023-12-18 at 12:54 +1000, Alistair Francis wrote: > On Fri, Dec 8, 2023 at 1:40 AM Rob Bradford > wrote: > > > > From: Weiwei Li > > > > Add support for amocas.w/d/q instructions whic

[PATCH 1/2] target/riscv: Add support for Zacas extension

From: Weiwei Li Add support for amocas.w/d/q instructions which are part of the ratified Zacas extension: https://github.com/riscv/riscv-zacas Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 2 + target

[PATCH 2/2] disas/riscv: Add amocas.[w,d,q] instructions

Signed-off-by: Rob Bradford --- disas/riscv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e9458e574b..8a546d5ea5 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -903,6 +903,9 @@ typedef enum { rv_op_vwsll_vv = 872, rv_op_vwsll_vx

[PATCH 0/2] Add support for (ratified) Zacas extension

iscv-software-src/riscv-tests/pull/492 Rob Bradford (1): disas/riscv: Add amocas.[w,d,q] instructions Weiwei Li (1): target/riscv: Add support for Zacas extension disas/riscv.c | 9 ++ target/riscv/cpu.c | 2 + target/riscv/cpu_c

Re: [PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Mon, 2023-10-23 at 12:02 +1000, Alistair Francis wrote: > On Thu, Oct 19, 2023 at 1:45 AM Rob Bradford > wrote: > > > > Using a mask instead of the number of PMU devices supports the > > accurate > > emulation of platforms that have a discontinuous set of PMU &

[PATCH v5 4/5] target/riscv: Add "pmu-mask" property to replace "pmu-num"

e order on the command line determines which takes precedence (later overwriting earlier.) Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 40 +- target/riscv/cpu_cfg.h | 2 +- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 15 +++

[PATCH v5 5/5] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- docs/about/deprecated.rst | 12 1 file changed, 12 insertions(+) diff --

[PATCH v5 3/5] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra

[PATCH v5 1/5] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

[PATCH v5 2/5] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/csr.c | 5 +++-- 1 file changed, 3

[PATCH v5 0/5] Support discontinuous PMU counters

f MAKE_32BIT_MASK() v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (5): target/riscv: Propagate error from PMU setup targe

[PATCH v4 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei --- docs/about/deprecated.rst | 12 1 file changed, 12 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated

[PATCH v4 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro

A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index

[PATCH v4 1/6] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

[PATCH v4 2/6] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions

[PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

e property is not explicitly by the user the property default value cannot be used so the default value must be set during the CPU object initialisation. If the "pmu-num" value is changed from the default then the mask will be generated from that to support the transition to "pmu-m

[PATCH v4 0/6] Support discontinuous PMU counters

dated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/riscv: Use existing PMU counter mask in FDT generation target/riscv: Add &

[PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- hw/riscv/virt.c

[PATCH v3 1/6] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

[PATCH v3 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro

A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 9253e5f17a..052d5b1164 100644 --- a

[PATCH v3 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei --- docs/about/deprecated.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated

[PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c

[PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

default Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu_cfg.h | 3 ++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 20 4 files changed, 22 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v3 0/6] Support discontinuous PMU counters

previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/risc

[PATCH v3 3/6] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei --- hw/riscv/virt.c| 2 +- target/riscv/pmu.c | 6

Re: [PATCH v2 5/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Thu, 2023-10-12 at 17:05 +0800, LIU Zhiwei wrote: >   > >   >   > On 2023/10/11 22:45, Rob Bradford wrote: >   >   > >   > > Using a mask instead of the number of PMU devices supports the > > accurate > > emulation of platforms that

[PATCH v2 2/6] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c

[PATCH v2 0/6] Support discontinuous PMU counters

ers though a "pmu-mask" property. v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propag

[PATCH v2 6/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford --- docs/about/deprecated.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 8b136320e2..

[PATCH v2 3/6] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford --- hw/riscv/virt.c| 2 +- target/riscv/pmu.c | 6 +- target/riscv/pmu.h

[PATCH v2 5/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

default Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu_cfg.h | 3 ++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 14 ++ 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v2 4/6] qemu/bitops.h: Add MAKE_32BIT_MASK macro

Add 32-bit version of mask generating macro and use it in the RISC-V PMU code. Signed-off-by: Rob Bradford --- include/qemu/bitops.h | 3 +++ target/riscv/pmu.c| 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index

[PATCH v2 1/6] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters

On Mon, 2023-10-09 at 11:00 -0700, Atish Kumar Patra wrote: > On Sun, Oct 8, 2023 at 5:58 PM Alistair Francis > wrote: > > > > On Wed, Oct 4, 2023 at 7:36 PM Rob Bradford > > wrote: > > > > > > Hi Atish, > > > > > > On Tue, 2023-1

Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters

Hi Atish, On Tue, 2023-10-03 at 13:25 -0700, Atish Kumar Patra wrote: > On Tue, Oct 3, 2023 at 5:51 AM Rob Bradford > wrote: > > > > There is no requirement that the enabled counters in the platform > > are > > continuously numbered. Add a "pmu-mask" pro

[PATCH 3/3] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c

[PATCH 1/3] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford --- target/riscv/cpu.c

[PATCH 2/3] target/riscv: Support discontinuous PMU counters

the number of bits set in the mask. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/pmu.c | 15 +-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9d79c20c1a..

[PATCH 0/3] Support discontinuous PMU counters

ers though a "pmu-mask" property. Rob Bradford (3): target/riscv: Propagate error from PMU setup target/riscv: Support discontinuous PMU counters target/riscv: Don't assume PMU counters are continuous target/riscv/cpu.c | 9 - target/riscv/cpu_cfg.h | 1 + ta

[PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

max value to these CSRs and upon subsequent read the appropriate number of bits for number of PMUs is enabled and the TM bit is zero in mcountinhibit. Signed-off-by: Rob Bradford --- target/riscv/csr.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v2] target/riscv: Fix LMUL check to use VLEN

must be supported." Elsewhere in the specification it makes clear that VLEN>=ELEN. >From inspection this new check allows: VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 VLEN=ELEN=32 1/2, 1/4 for SEW >=8 Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions")

Re: [PATCH] target/riscv: Fix LMUL check to use minimum SEW

On Thu, 2023-07-06 at 21:22 +0800, Weiwei Li wrote: > > On 2023/7/6 18:44, Rob Bradford wrote: > > The previous check was failing with: > > > > ELEN = 64 SEW = 16 and LMUL = 1/8 (encoded as 5) which is a valid > > combination. > > > > Fix the check to

[PATCH] target/riscv: Fix LMUL check to use minimum SEW

al LMULs of 1/2, 1/4, and 1/8 must be supported." >From inspection this new check allows: ELEN=64 1/2, 1/4, 1/8 (encoded as 7, 6, 5 respectfully) ELEN=32 1/2, 1/4 (encoded as 7 and 6 respectfully) Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") S

Re: [PATCH 1/2] target/riscv: Add Zacas ISA extension support

On Fri, 2023-06-02 at 23:04 +0800, Weiwei Li wrote: > > On 2023/6/2 20:16, Rob Bradford wrote: > > This commit adds support for the the amocas.{w,d,q} instructions > > behind > > a new property to enable that instruction. > > > > Signed-off-by: Rob Bradford

Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

On Thu, 2023-06-15 at 21:14 +0800, Weiwei Li wrote: > > On 2023/6/15 20:58, Rob Bradford wrote: > > On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote: > > > Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. > > > Add require check for BF16 extensions. > &g

Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote: > Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. > Add require check for BF16 extensions. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza > --- >  target/riscv/cpu.c | 20 ++

Re: [PATCH 2/2] disas/riscv: Add support for amocas.{w, d, q} instructions

On Fri, 2 Jun 2023 at 13:17, Rob Bradford wrote: > /* structures */ > @@ -2123,6 +2126,9 @@ const rv_opcode_data opcode_data[] = { > { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, > { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL

[PATCH 2/2] disas/riscv: Add support for amocas.{w,d,q} instructions

Signed-off-by: Rob Bradford --- disas/riscv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index d597161d46..dbed2010f8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -964,6 +964,9 @@ typedef enum { rv_op_cm_jalt = 788, rv_op_czero_eqz

[PATCH 1/2] target/riscv: Add Zacas ISA extension support

This commit adds support for the the amocas.{w,d,q} instructions behind a new property to enable that instruction. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 4 + target/riscv/cpu.h | 1 + target/riscv/insn32.decode

RFC: target/riscv: Add support for Zacas extension

The Zacas[1] extension is a proposed unprivileged ISA extension for adding support for atomic compare-and-swap. Since this extension is not yet frozen (although no significant changes are expected) these patches are RFC/informational. Cheers, Rob [1] - https://github.com/riscv/riscv-zacas/blob/m

Re: [Qemu-devel] QEMU/NEMU boot time with several x86 firmwares

,kernel_irqchip,nvdimm -cpu host -m > 512,maxmem=1G,slots=1 -smp 1 -kernel $KERNEL -append 'root=/dev/pmem0 > ro console=hvc0' -vga none -display none -no-user-config -nodefaults > -object memory-backend-file,id=mem0,share,mem- > path=$ROOTFS,size=$ROOTFS_SIZE > -dev

Re: [Qemu-devel] QEMU/NEMU boot time with several x86 firmwares

Hi Stefano, On Mon, 2018-11-26 at 17:40 +0100, Stefano Garzarella wrote: > Hi Samuel, Rob, > I'm proceeding to compare several x86 firmwares in order to > understand > which suits better with -kernel option to have a fast boot with > QEMU/NEMU. > > For your use cases, what boot time do you expect