Re: [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform

Hello Alistair, Could you please comment? I'd like to know if this version of patch set need any more work. Thanks & Regards, Ran On 2025/4/25 20:17, Ran Wang wrote: This serial adds Xiangshan Kunminghu CPU and its FPGA prototype platform, which include UART, CLINT, IMSIC, and APLI

[PATCH v4 0/2] riscv: Add Kunminghu CPU and platform

This serial adds Xiangshan Kunminghu CPU and its FPGA prototype platform, which include UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Patches based on alistair/riscv-to-apply.next Huang Borong (2): target/riscv: Add BOSC's Xiangs

[PATCH v4 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype

aoqing Signed-off-by: Yang Wang Signed-off-by: Yu Hu Signed-off-by: Ran Wang Signed-off-by: Borong Huang <3543977...@qq.com> Reviewed-by: Daniel Henrique Barboza --- MAINTAINERS | 7 + configs/devices/riscv64-softmmu/default.mak | 1 + docs/system/ris

[PATCH v4 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

orized based on four RISC-V specifications: Volume I: Unprivileged Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The extensions within each category are organized according to the chapter order in the specifications. Signed-off-by: Yu Hu Signed-off-by: Ran Wang Signed-off-by:

Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

Hi Alistair On 2025/4/24 18:49, Alistair Francis wrote: On Tue, Apr 8, 2025 at 12:23 PM Huang Borong wrote: Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source, high-performance RISC-V processor. More details can be found at: +cpu->cfg.ext_ssaia = true; + +/* RVA23 Pr