2025-06-25T14:24:25+08:00, Jim Shu :
> Hi Radim,
>
> Does your patchset want to resolve the same issue as my sstc patch [1]?
> My sstc patchset has been merged to "riscv-to-apply.next".
Yeah, I wasn't aware where patches go in the QEMU land.
> Maybe you can review
2025-06-23T18:39:02-03:00, Daniel Henrique Barboza :
> Hi Radim,
>
> It seems like this patch is breaking 'make check-functional':
That is a nice command to know of, thanks!
> 12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT
> 90.
report.
Thanks.
Radim Krčmář (2):
target/riscv: disable *stimecmp interrupts without *envcfg.STCE
target/riscv: disarm timer when writing past value
target/riscv/csr.c | 12
target/riscv/time_helper.c | 12
2 files changed, 24 insertions(+)
--
2.49.0
timer is disarmed.
Call the *stimecmp CSR update functions when *envcfg.STCE is toggled,
because the *ip CSRs need to immediately reflect the new behavior.
Fixes: 43888c2f1823 ("target/riscv: Add stimecmp support")
Signed-off-by: Radim Krčmář
---
target/riscv/csr.c | 12 +
There is no need to keep the timer running when writing a past value to
the *stimecmp. The behavior was correct before, but I think it makes a
bit more sense like this.
Signed-off-by: Radim Krčmář
---
target/riscv/time_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv
2025-04-28T09:00:55+02:00, Andrew Jones :
> On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote:
>> This patch adds host satp mode while kvm/host cpu satp mode is not
>> set.
>
> Huh, the KVM side[1] was written for this purpose, but it appears we never
> got a QEMU side merged.
>
> [1] commi
2025-04-28T14:08:59+02:00, Andrew Jones :
> On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote:
>> 2025-04-28T09:00:55+02:00, Andrew Jones :
>> > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote:
>> >> This patch adds host satp mode while kvm/host
2018-08-28 11:58-0300, Eduardo Habkost:
> On Sat, Aug 25, 2018 at 08:19:47PM +0800, Peng Hao wrote:
> > add coalesced_pio's struct and KVM_CAP_COALESCED_PIO header.
> >
> > Signed-off-by: Peng Hao
>
> What's the status of the corresponding KVM header patch?
I got a minor request to improve comp
2018-02-28 22:18+, Moger, Babu:
> > -Original Message-
> > From: Radim Krčmář [mailto:rkrc...@redhat.com]
> > Sent: Wednesday, February 28, 2018 12:24 PM
> > To: Moger, Babu
> > Cc: pbonz...@redhat.com; r...@twiddle.net; ehabk...@redhat.com;
>
2018-03-01 15:55+, Moger, Babu:
> Radim, Thanks for your comments. I am working on the changes.
> But, I need few clarifications on your comments. Please see inline.
>
> > -Original Message-
> > From: Radim Krčmář [mailto:rkrc...@redhat.com]
> > Sent: Wedn
2018-02-23 21:30-0500, Babu Moger:
> From: Stanislav Lanci
>
> Adds information about cache size and topology from cpuid 0x801D leaf
> for different cache types on AMD processors.
>
> Signed-off-by: Stanislav Lanci
> Signed-off-by: Babu Moger
> ---
> diff --git a/target/i386/cpu.c b/target
2018-02-23 21:30-0500, Babu Moger:
> From: Stanislav Lanci
>
> Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
> feature is supported. This is required to support hyperthreading
> feature on AMD CPUS. These are supported via CPUID_8000_001E extended
> functions.
>
> Signed-of
2018-02-23 21:30-0500, Babu Moger:
> Changed KVM_CPUID_FLAG_SIGNIFCANT_INDEX to KVM_CPUID_FLAG_SIGNIFICANT_INDEX
>
> Signed-off-by: Babu Moger
> ---
> linux-headers/asm-x86/kvm.h | 2 +-
> target/i386/kvm.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/li
This should primarily go to the qemu devel list. I've Cc'd it, but
reposting would be safer, thanks.
2018-02-02 10:21+0530, P J P:
> From: Prasad J Pandit
>
> When updating message signalled interrupt(MSI) route in routine
> kvm_irqchip_update_msi_route, device parameter could be null.
> Add c
2017-11-22 18:28-0200, Eduardo Habkost:
> On Wed, Nov 22, 2017 at 07:09:08PM +0100, Radim Krčmář wrote:
> > QEMU saves only 8 bits of APIC LDR, which means that it does not support
> > x2APIC. The correct way of fixing this would be to save and restore the
> > full 32 bit
2017-11-22 20:26+0100, Paolo Bonzini:
> On 22/11/2017 19:09, Radim Krčmář wrote:
> > QEMU saves only 8 bits of APIC LDR, which means that it does not support
> > x2APIC. The correct way of fixing this would be to save and restore the
> > full 32 bit register, but because x2A
with patch 5849d75a5c9b
("KVM: lapic: Fixup LDR on load in x2apic").
Reported-by: Dr. David Alan Gilbert
Reported-by: Yiqian Wei
Signed-off-by: Radim Krčmář
---
I haven't tested that it actually fixes the bug,
https://bugzilla.redhat.com/show_bug.cgi?id=1502591.
hw/i386/
2017-08-10 15:16-0300, Eduardo Habkost:
> On Thu, Aug 10, 2017 at 02:41:03PM +0200, Radim Krčmář wrote:
> > 2017-08-10 19:02+0800, Lan Tianyu:
> > > On 2017年08月10日 18:26, Daniel P. Berrange wrote:
> > >> On Thu, Aug 10, 2017 at 06:08:07PM +0800, Lan Tianyu wrote:
&g
2017-08-10 19:02+0800, Lan Tianyu:
> On 2017年08月10日 18:26, Daniel P. Berrange wrote:
>> On Thu, Aug 10, 2017 at 06:08:07PM +0800, Lan Tianyu wrote:
>>> Intel Xeon phi chip will support 352 logical threads. For HPC
>>> usage case, it will create a huge VM with vcpus number as same as host
>>> cpus.
2017-06-20 20:14-0700, Wanpeng Li:
> From: Wanpeng Li
>
> This patch adds async pf flag to KVM_GET/SET_VCPU_EVENTS interface.
>
> Signed-off-by: Wanpeng Li
> ---
> diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
> @@ -300,6 +301,7 @@ struct kvm_vcpu_events {
>
2017-06-13 20:00+0800, Jay Zhou:
> On 2017/6/13 3:52, Radim Krčmář wrote:
> > If you get a timestamp from KVM_GET_CLOCK() and pass that to
> > KVM_SET_CLOCK(), then kvmclock should not jump backwards anymore
> > (it could before 4.9, but only if the host had stable tsc).
>
2017-06-12 21:30+0800, Jay Zhou:
> Guest using kvmclock will be hanged when migrating from unstable
> tsc host to stable tsc host occasionally.
> Sometimes, the tsc timestamp saved at the source side will be
> backward when the guest stopped, and this value is transferred
> to the destination side.
2017-06-12 21:23+0800, Jay Zhou:
> Guest using kvmclock will be hanged when migrating from unstable
> tsc host to stable tsc host occasionally.
> Sometimes, the tsc timestamp saved at the source side will be
> backward when the guest stopped, and this value is transferred
> to the destination side.
2017-05-26 13:16+0800, Zhuangyanying:
> From: ZhuangYanying
>
> When spin_lock_irqsave() deadlock occurs inside the guest, vcpu threads,
> other than the lock-holding one, would enter into S state because of
> pvspinlock. Then inject NMI via libvirt API "inject-nmi", the NMI could
> not be inject
Please use tags in patches.
We usually begin the subject with "KVM: x86:" when touching
arch/x86/kvm/x86.c.
2017-05-24 13:48+0800, Zhuangyanying:
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> @@ -8394,7 +8394,8 @@ static inline bool kvm_vcpu_has_events(struct kvm_vcpu
> *vcpu)
>
[Cc qemu-devel as we've gone off-topic]
2017-04-04 15:15+0200, Alexander Graf:
> On 04/04/2017 03:13 PM, Radim Krčmář wrote:
>> 2017-04-04 14:51+0200, Alexander Graf:
>> > Please see my patch to force enable CPUID bits ;).
>> Nice. MWAIT could also use setting of
2017-03-22 18:06+0200, Michael S. Tsirkin:
> On Wed, Mar 22, 2017 at 04:59:06PM +0100, Radim Krčmář wrote:
>> QEMU does not allocate based on machine's max_cpus, but only uses it to
>> limit the maximum selected by user and the actual limit of VCPUs is
>> enfoced by other
d
the other two billion VCPU won't be needed for a while, so we can ignore
possible bugs by using signed max.
Signed-off-by: Radim Krčmář
---
Should the 2.9 machine type still have 288?
---
hw/i386/pc_q35.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_q3
2017-01-05 10:35+0800, Peter Xu:
> On Wed, Jan 04, 2017 at 03:55:42PM +0100, Radim Krčmář wrote:
>> > I didn't notice the "-n" parameter for "wait", otherwise I won't
>> > bother using SIGUSR1 at all. :)
>>
>> (Btw. why couldn
2017-01-05 11:07+0800, Peter Xu:
> On Wed, Jan 04, 2017 at 04:09:39PM +0100, Radim Krčmář wrote:
>> 2017-01-03 18:10+0800, Peter Xu:
>> > run_task.sh is getting slow. This patch is trying to make it faster by
>> > running the tests concurrently.
>> >
>>
sh | 75s |
>| run_test.sh -j8 | 27s |
>|-+---|
>
> Suggested-by: Radim Krčmář
> Signed-off-by: Peter Xu
> ---
> run_tests.sh | 12 ++--
> scripts/functions.bash | 15 ++-
> scripts/global.bash| 11 +
2017-01-03 10:45+0800, Peter Xu:
> On Mon, Jan 02, 2017 at 09:18:24PM +0100, Radim Krčmář wrote:
>> 2017-01-01 18:34+0800, Peter Xu:
>> > diff --git a/scripts/functions.bash b/scripts/functions.bash
>> Couldn't the queue be much simpler ...
>>
>> &
2017-01-02 18:07+0100, Paolo Bonzini:
> On 01/01/2017 11:34, Peter Xu wrote:
>> run_tests.sh is getting slower. Maybe it's time to let it run faster.
>> An obvious issue is that, we were running the tests sequentially in
>> the past.
>>
>> This series provides another new "-j" parameter. "-j 8" me
2017-01-01 18:34+0800, Peter Xu:
> run_task.sh is getting slow. This patch is trying to make it faster by
> running the tests concurrently.
>
> First of all, we provide a new parameter "-j" for the run_tests.sh,
> which can be used to specify how many run queues we want for the tests.
> When "-j"
2016-11-21 18:22+, Andre Przywara:
> Both environment variables seem to be standard in cross-compilation
> environments, especially with Linux.
> Let the configure script take those into account when setting the default
> values for --arch and --cross-prefix. Explicitly specifying the latter
>
2016-11-04 16:29-0200, Marcelo Tosatti:
> On Fri, Nov 04, 2016 at 06:34:20PM +0100, Radim Krčmář wrote:
>> 2016-11-04 14:24-0200, Marcelo Tosatti:
>> > On Fri, Nov 04, 2016 at 04:48:28PM +0100, Radim Krčmář wrote:
>> >> 2016-11-04 16:33+0100, Paolo Bonzini:
>
2016-11-04 15:07-0200, Marcelo Tosatti:
> On Fri, Nov 04, 2016 at 04:25:23PM +0100, Radim Krčmář wrote:
>> > +/*
>> > + * Transition from VM-running to VM-stopped via migration?
>> > + * Record when the VM was stopped.
>> > +
2016-11-04 14:24-0200, Marcelo Tosatti:
> On Fri, Nov 04, 2016 at 04:48:28PM +0100, Radim Krčmář wrote:
>> 2016-11-04 16:33+0100, Paolo Bonzini:
>> > On 04/11/2016 16:25, Radim Krčmář wrote:
>> >>> >
>> >>> > +if (s->advance_
2016-11-04 16:57+0100, Paolo Bonzini:
> On 04/11/2016 16:48, Radim Krčmář wrote:
>> 2016-11-04 16:33+0100, Paolo Bonzini:
>>> On 04/11/2016 16:25, Radim Krčmář wrote:
>>>>>>
>>>>>> +if (s->advance_clock && s->clock +
2016-11-04 16:33+0100, Paolo Bonzini:
> On 04/11/2016 16:25, Radim Krčmář wrote:
>>> >
>>> > +if (s->advance_clock && s->clock + s->advance_clock > s->clock) {
>>> > +s->clock += s->advance_clock;
&g
2016-11-04 07:43-0200, Marcelo Tosatti:
> This patch, relative to pre-copy migration codepath,
> measures the time between vm_stop() and pre_save(),
> which includes copying the remaining RAM to destination,
> and advances the clock by that amount.
>
> In a VM with 5 seconds downtime, this reduce
2016-10-19 11:55-0200, Eduardo Habkost:
> On Wed, Oct 19, 2016 at 03:27:52PM +0200, Radim Krčmář wrote:
>> 2016-10-18 19:05-0200, Eduardo Habkost:
>> > On Tue, Oct 18, 2016 at 10:52:14PM +0200, Radim Krčmář wrote:
>> > [...]
>> >> The main problem is
2016-10-18 19:05-0200, Eduardo Habkost:
> On Tue, Oct 18, 2016 at 10:52:14PM +0200, Radim Krčmář wrote:
> [...]
>> The main problem is that QEMU changes virtual_tsc_khz when migrating
>> without hardware scaling, so KVM is forced to get nanoseconds wrong ...
>>
>> If
2016-10-18 15:09-0200, Marcelo Tosatti:
> On Tue, Oct 18, 2016 at 03:41:03PM +0200, Paolo Bonzini wrote:
>> On 18/10/2016 01:58, Marcelo Tosatti wrote:
>> > > We should also blacklist the TSC deadline timer when invtsc is not
>> > > available.
>> >
>> > Actually, a nicer fix would be to check the d
2016-10-18 12:56-0200, Eduardo Habkost:
> On Fri, Oct 14, 2016 at 01:21:55PM +0200, Igor Mammedov wrote:
>> Signed-off-by: Igor Mammedov
>> ---
>> v4:
>> - restore kvm_has_x2apic_api() and use it to avoid side-effects
>>of kvm_enable_x2apic(). x2APIC API will be enabled by iommu
>>if it's
2016-10-17 21:58-0200, Marcelo Tosatti:
> On Mon, Oct 17, 2016 at 07:11:01PM -0200, Eduardo Habkost wrote:
>> On Mon, Oct 17, 2016 at 06:24:38PM +0200, Paolo Bonzini wrote:
>> > On 17/10/2016 16:50, Radim Krčmář wrote:
>> > > 2016-10-17 07:47-0200, Marcelo Tosatti
2016-10-17 18:24+0200, Paolo Bonzini:
> On 17/10/2016 16:50, Radim Krčmář wrote:
>> 2016-10-17 07:47-0200, Marcelo Tosatti:
>>> On Fri, Oct 14, 2016 at 06:20:31PM -0300, Eduardo Habkost wrote:
>>>> I have been wondering: should we allow live migration with the
&g
2016-10-18 15:36+0200, Radim Krčmář:
> 2016-10-17 18:24+0200, Paolo Bonzini:
>> We should also blacklist the TSC deadline timer when invtsc is not
>> available.
>
> True.
>
> I was thinking that with Wanpeng's VMX preemption patches, we might not
> need the
2016-10-17 15:20-0200, Marcelo Tosatti:
> On Mon, Oct 17, 2016 at 04:50:09PM +0200, Radim Krčmář wrote:
>> 2016-10-17 07:47-0200, Marcelo Tosatti:
>> > On Fri, Oct 14, 2016 at 06:20:31PM -0300, Eduardo Habkost wrote:
>> >> I have been wondering: should we allow live m
2016-10-17 07:47-0200, Marcelo Tosatti:
> On Fri, Oct 14, 2016 at 06:20:31PM -0300, Eduardo Habkost wrote:
>> I have been wondering: should we allow live migration with the
>> invtsc flag enabled, if TSC scaling is available on the
>> destination?
>
> TSC scaling and invtsc flag, yes.
Yes, if we
2016-10-14 13:21+0200, Igor Mammedov:
> Signed-off-by: Igor Mammedov
> ---
Reviewed-by: Radim Krčmář
> v4:
> - restore kvm_has_x2apic_api() and use it to avoid side-effects
>of kvm_enable_x2apic(). x2APIC API will be enabled by iommu
>if it's present or n
2016-10-13 11:52+0200, Igor Mammedov:
> SDM: x2APIC State Transitions:
> State Changes From xAPIC Mode to x2APIC Mode
> "
> Any APIC ID value written to the memory-mapped
> local APIC ID register is not preserved
> "
>
> Signed-off-by: Igor Mammedov
2016-10-13 11:52+0200, Igor Mammedov:
> Signed-off-by: Igor Mammedov
> ---
> v4:
> - drop kvm_has_x2apic_api() and reuse kvm_enable_x2apic() instead
> ---
Reviewed-by: Radim Krčmář
> hw/i386/kvm/apic.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
2016-10-13 11:52+0200, Igor Mammedov:
> it would prevent starting guest with incorrect configs
> where interrupts couldn't be delivered to CPUs with
> APIC IDs > 254.
off-by-one.
> Signed-off-by: Igor Mammedov
> ---
Reviewed-by: Radim Krčmář
> hw/i386/pc.c |
2016-10-13 15:24+0200, Igor Mammedov:
> along with it for machine versions 2.7 and older keep
> it at 255.
>
> Signed-off-by: Igor Mammedov
> ---
Seems nicer than touching max_cpus in pc_machine_class_init(),
Reviewed-by: Radim Krčmář
> Forgot to inlude the last patch th
ways, and make it the default for old machine types.
A user can enable the buggy mode it with "x-buggy-eim=on".
Signed-off-by: Radim Krčmář
---
v5:
* squash with the patch that added compat property:
v5: rename property to x-buggy-eim [Eduardo and Michael]
v4:
* use a d
Assume that KVM would have returned the same on subsequent runs.
Abstract the memoizaiton pattern into macros and call it memorize as
adding the r makes it less obscure.
Reviewed-by: Igor Mammedov
Signed-off-by: Radim Krčmář
---
v5: r-b Igor
v4:
* changed the name to memorize [Igor]
* remove
ested-by: Eduardo Habkost
Reviewed-by: Eduardo Habkost
Reviewed-by: Peter Xu
Signed-off-by: Radim Krčmář
---
v5: r-b Eduardo and Peter
v4: do not use private class attribute [Eduardo]
v3: completely rewrite the mechanism [Eduardo]
v2: assert() instead of error_report() and exit() [Peter]
---
hw
The MMIO based interface to APIC doesn't work well with MSIs that have
upper address bits set (remapped x2APIC MSIs). A specialized interface
is a quick and dirty way to avoid the shortcoming.
Reviewed-by: Igor Mammedov
Reviewed-by: Peter Xu
Signed-off-by: Radim Krčmář
---
v5: r-b Peter
v4: http://lists.nongnu.org/archive/html/qemu-devel/2016-10/msg00698.html
v5 is one patch shorter as it merged two patches from v4 into [6/7].
The x2APIC mode works on >=2.8 machine types with this series and <2.7
remain compatible (aka broken).
Radim Krčmář (7):
apic: add
* there no point in configuring the device if realization is going to
fail, so move the check to the beginning,
* create a separate function for the check,
* use error_setg() instead error_report().
Reviewed-by: Igor Mammedov
Reviewed-by: Peter Xu
Signed-off-by: Radim Krčmář
---
v5: r-b
The default (auto) emulates the current behavior.
A user can now control EIM like
-device intel-iommu,intremap=on,eim=off
Reviewed-by: Igor Mammedov
Reviewed-by: Peter Xu
Signed-off-by: Radim Krčmář
---
v5: r-b Peter
v4:
* r-b Igor
* added an example to the commit message
v3:
* use
.
Reviewed-by: Peter Xu
Signed-off-by: Radim Krčmář
---
v5: added r-b Peter, removed r-b Igor (added by mistake)
v4: r-b Igor
v2: fix build with enabled DEBUG_INTEL_IOMMU [Peter]
---
hw/i386/intel_iommu.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a
2016-10-08 15:21+0800, Peter Xu:
> On Wed, Oct 05, 2016 at 03:06:55PM +0200, Radim Krčmář wrote:
>
> [...]
>
>> @@ -2472,10 +2473,22 @@ static bool vtd_decide_config(IntelIOMMUState *s,
>> Error **errp)
>> }
>>
>> if (s->intr_eim =
2016-10-08 14:37+0800, Peter Xu:
> On Wed, Oct 05, 2016 at 03:06:51PM +0200, Radim Krčmář wrote:
>> The MMIO based interface to APIC doesn't work well with MSIs that have
>> upper address bits set (remapped x2APIC MSIs). A specialized interface
>> is a quick and dirty wa
2016-10-08 11:31+0800, Herongguang (Stephen):
> On 2016/9/23 12:59, herongguang wrote:
>> From: He Rongguang
>>
>> handle KVM_VCPUEVENT_VALID_SMM properly, or kvm-kmod/kernel will crash
>> in migration destination in gfn_to_rmap() since kvm_memslots_for_spte_role
>> is false, whilst (vcpu->arch.h
2016-10-07 15:05+0200, Igor Mammedov:
> On Wed, 5 Oct 2016 15:06:52 +0200
> Radim Krčmář wrote:
>
>> The MMIO interface to APIC only allowed 8 bit addresses, which is not
>> enough for 32 bit addresses from EIM remapping.
>> Intel stored upper 24 bits in the high M
2016-10-06 11:51-0300, Eduardo Habkost:
> On Wed, Oct 05, 2016 at 03:06:56PM +0200, Radim Krčmář wrote:
>> Signed-off-by: Radim Krčmář
>> ---
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> @@ -2015,6 +2015,7 @@ static Property vtd_properties[] = {
2016-10-06 18:33+0300, Michael S. Tsirkin:
> On Thu, Oct 06, 2016 at 11:51:42AM -0300, Eduardo Habkost wrote:
>> On Wed, Oct 05, 2016 at 03:06:56PM +0200, Radim Krčmář wrote:
>> > QEMU 2.7 allowed EIM even in configurations that were forbidden in the
>> > last patch be
2016-10-05 15:35+0200, Radim Krčmář:
> This series performs a simple replacement of
> object_new(object_class_get_name(class)) by object_new_with_class(class)
> in the spirit of existing object_new_with_type().
This series applies after recently posted
[PATCH v4 1/8] apic: a
eas Färber"
Cc: Richard Henderson
Cc: Paolo Bonzini
Cc: Eduardo Habkost
Cc: Alexander Graf
Cc: Max Filippov
Cc: qemu-...@nongnu.org
Radim Krčmář (2):
qom: add object_new_with_class()
coccinelle: use object_new_with_class() in obvious cases
hw/arm/exynos4210.c
object_new_with_object_class() was a close contender for the name, but
it is longer, the type system will catch possible errors, and the only
reasonable replacement would be a polymorphic function that would not
break existing users.
Signed-off-by: Radim Krčmář
---
include/qom/object.h | 12
object_new_with_class(class) does a better job than
object_new(object_class_get_name(class)), because
object_class_get_name() lost the class->type and object_new() looked it
up again from the name.
Manually changed vl.c to fit into 80 character line.
Signed-off-by: Radim Krčmář
---
hw/
.
Reviewed-by: Igor Mammedov
Signed-off-by: Radim Krčmář
---
v4: r-b Igor
v2: fix build with enabled DEBUG_INTEL_IOMMU [Peter]
---
hw/i386/intel_iommu.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index
can enable the buggy mode it with "buggy_eim=on", which is weird,
but I don't know how to add a private property.
Signed-off-by: Radim Krčmář
---
v4:
* use a device property [Igor]
* clarify the last sentence of the commit message
v3: shorten the code [Peter]
---
hw/i38
Assume that KVM would have returned the same on subsequent runs.
Abstract the memoizaiton pattern into macros and call it memorize as
adding the r makes it less obscure.
Signed-off-by: Radim Krčmář
---
v4:
* changed the name to memorize [Igor]
* remove useless underscores in macro arguments
ested-by: Eduardo Habkost
Signed-off-by: Radim Krčmář
---
v4: do not use private class attribute [Eduardo]
v3: completely rewrite the mechanism [Eduardo]
v2: assert() instead of error_report() and exit() [Peter]
It still looks horrible, so I'll be glad for any advice.
And what is CONFIG
* there no point in configuring the device if realization is going to
fail, so move the check to the beginning,
* create a separate function for the check,
* use error_setg() instead error_report().
Reviewed-by: Igor Mammedov
Signed-off-by: Radim Krčmář
---
v4: r-b Igor
v3:
* use error_setg
The default (auto) emulates the current behavior.
A user can now control EIM like
-device intel-iommu,intremap=on,eim=off
Reviewed-by: Igor Mammedov
Signed-off-by: Radim Krčmář
---
v4:
* r-b Igor
* added an example to the commit message
v3:
* use error_setg [Paolo]
* shorten the code
g leads to aliasing so interrupts were being delivered to
incorrect VCPUs.
KVM_X2APIC_API is the feature that allows us to enable eim for KVM.
Signed-off-by: Radim Krčmář
---
v4: be more specific in the comment [Igor]
v3:
* use error_setg [Paolo]
* shorten the code [Peter]
v2:
* adapt to ne
ection breaker; see the discussion under [v2 7/7] for details
(http://lists.nongnu.org/archive/html/qemu-devel/2016-09/msg07795.html).
Radim Krčmář (8):
apic: add global apic_get_class()
apic: add send_msi() to APICCommonClass
intel_iommu: pass whole remapped addresses to apic
intel_iommu
The MMIO based interface to APIC doesn't work well with MSIs that have
upper address bits set (remapped x2APIC MSIs). A specialized interface
is a quick and dirty way to avoid the shortcoming.
Reviewed-by: Igor Mammedov
Signed-off-by: Radim Krčmář
---
v4: r-b Igor
v2: change apic_send_msi
2016-10-03 13:03-0300, Eduardo Habkost:
> On Fri, Sep 30, 2016 at 06:10:06PM +0200, Radim Krčmář wrote:
>> Every configuration has only up to one APIC class and we'll be extending
>> the class with a function that can be called without an instanced
>> object, so a dir
2016-10-04 14:18+0200, Igor Mammedov:
> On Fri, 30 Sep 2016 18:10:12 +0200
> Radim Krčmář wrote:
>> QEMU 2.7 allowed EIM even in configurations that were forbidden in the
>> last patch because they were not working, like old KVM or userspace
>> APIC. In order to keep ba
2016-10-04 13:33+0200, Igor Mammedov:
> On Fri, 30 Sep 2016 18:10:13 +0200
> Radim Krčmář wrote:
>> Assume that KVM would have returned the same on subsequent runs.
>> Abstract the memoizaiton pattern into macros.
> s/memoi/memori/i
> Throughout whole patch
The pattern
we keep it
enabled only for the KVM APIC; unconditionally, because making the
option depend on KVM version would be a maintanance burden.
Signed-off-by: Radim Krčmář
---
v3:
* use error_setg [Paolo]
* shorten the code [Peter]
v2:
* adapt to new intr_eim parameter
* provide first linux versio
The MMIO based interface to APIC doesn't work well with MSIs that have
upper address bits set (remapped x2APIC MSIs). A specialized interface
is a quick and dirty way to avoid the shortcoming.
Signed-off-by: Radim Krčmář
---
v2: change apic_send_msi() to accept MSIMessage [Igor]
---
hw
Assume that KVM would have returned the same on subsequent runs.
Abstract the memoizaiton pattern into macros.
Signed-off-by: Radim Krčmář
---
target-i386/kvm.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index
The default (auto) emulates the current behavior.
Signed-off-by: Radim Krčmář
---
v3:
* use error_setg [Paolo]
* shorten the code [Peter]
---
hw/i386/intel_iommu.c | 24 +---
include/hw/i386/intel_iommu.h | 1 +
2 files changed, 22 insertions(+), 3 deletions
ested-by: Eduardo Habkost
Signed-off-by: Radim Krčmář
---
v2: assert() instead of error_report() and exit() [Peter]
v3: completely rewrite the mechanism [Eduardo]
It still looks horrible, so I'll be glad for any advice.
And what is CONFIG_USER_ONLY?
---
hw/intc/apic_common.c | 1
.
Signed-off-by: Radim Krčmář
---
v2: fix build with enabled DEBUG_INTEL_IOMMU [Peter]
---
hw/i386/intel_iommu.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 9f4e64af1ad5..c39b62b898d8 100644
--- a/hw
QEMU 2.7 allowed EIM even in configurations that were forbidden in the
last patch because they were not working, like old KVM or userspace
APIC. In order to keep backward compatibility, we again allow guests to
misbehave in non-obvious ways, and make it the default.
Signed-off-by: Radim Krčmář
* there no point in configuring the device if realization is going to
fail, so move the check to the beginning,
* create a separate function for the check,
* use error_setg() instead error_report().
Signed-off-by: Radim Krčmář
---
v3:
* use error_setg [Paolo]
* create a new function [Peter
ection breaker; see the discussion under [v2 7/7] for details
(http://lists.nongnu.org/archive/html/qemu-devel/2016-09/msg07795.html).
Radim Krčmář (8):
apic: add global apic_get_class()
apic: add send_msi() to APICCommonClass
intel_iommu: pass whole remapped addresses to apic
intel_iommu
2016-09-30 13:13+0800, Peter Xu:
> On Thu, Sep 29, 2016 at 01:23:27PM +0200, Radim Krčmář wrote:
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> @@ -2466,6 +2472,18 @@ static void vtd_realize(DeviceState *dev, Error
>> **errp)
>> exit(1);
&
2016-09-30 13:40+0800, Peter Xu:
> On Thu, Sep 29, 2016 at 01:23:29PM +0200, Radim Krčmář wrote:
>
> [...]
>
>> @@ -2481,11 +2482,14 @@ static void vtd_realize(DeviceState *dev, Error
>> **errp)
>> if (s->intr_eim == ON_OFF_AUTO_AUTO && !x86_iommu-&
2016-09-29 18:06+0200, Igor Mammedov:
> On Thu, 29 Sep 2016 15:18:36 +0200
> Paolo Bonzini wrote:
>> On 29/09/2016 13:23, Radim Krčmář wrote:
>> > Cluster x2APIC cannot work without KVM's x2apic API when the maximal
>> > APIC ID is greater than 8 and only KV
2016-09-29 15:19+0200, Paolo Bonzini:
> On 29/09/2016 13:23, Radim Krčmář wrote:
>> QEMU 2.7 allowed EIM even in configurations that were forbidden in the
>> last patch because they were not working, like old KVM or userspace
>> APIC. In order to keep backward compatibility,
2016-09-29 11:53-0300, Eduardo Habkost:
> On Thu, Sep 29, 2016 at 01:23:23PM +0200, Radim Krčmář wrote:
>> Every configuration has only up to one APIC class and we'll be extending
>> the class with a function that can be called without an instanced
>> object, so a dir
we keep it
enabled only for the KVM APIC; unconditionally, because making the
option depend on KVM version would be a maintanance burden.
Signed-off-by: Radim Krčmář
---
v2:
* adapt to new intr_eim parameter
* provide first linux version that has x2apic api
* disable QEMU's LAPIC
---
hw/i38
1 - 100 of 254 matches
Mail list logo
