From: Prasad Singamsetty
qemu command fails to process -overcommit option. Add the missing
call to qemu_add_opts() in vl.c.
Signed-off-by: Prasad Singamsetty
---
vl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/vl.c b/vl.c
index 16b913f9d5..12d27fa028 100644
--- a/vl.c
+++ b/vl.c
On 1/10/2018 6:46 PM, Liu, Yi L wrote:
-Original Message-
From: Qemu-devel [mailto:qemu-devel-bounces+yi.l.liu=intel@nongnu.org] On
Behalf Of Prasad Singamsetty
Sent: Thursday, January 11, 2018 8:06 AM
To: Liu, Yi L
Cc: ehabk...@redhat.com; m...@redhat.com; konrad.w...@oracle.com
Hi Yi L,
On 12/1/2017 3:29 AM, Liu, Yi L wrote:
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
iova address width. This patch provides a new parameter (x-aw-bits
On 12/1/2017 3:23 AM, Liu, Yi L wrote:
On Tue, Nov 14, 2017 at 06:13:49PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
host/iova address width so number of macros use hard coded values based
on that
On 11/30/2017 8:43 PM, Peter Xu wrote:
On Thu, Nov 30, 2017 at 11:12:48AM -0800, Prasad Singamsetty wrote:
On 11/30/2017 10:56 AM, Michael S. Tsirkin wrote:
On Thu, Nov 30, 2017 at 10:33:50AM -0800, Prasad Singamsetty wrote:
On 11/29/2017 7:25 PM, Peter Xu wrote:
On Wed, Nov 29, 2017
On 11/29/2017 7:25 PM, Peter Xu wrote:
On Wed, Nov 29, 2017 at 01:05:22PM -0800, Prasad Singamsetty wrote:
Thanks Michael. Some comments below.
On 11/28/2017 9:32 AM, Michael S. Tsirkin wrote:
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad
On 11/30/2017 10:56 AM, Michael S. Tsirkin wrote:
On Thu, Nov 30, 2017 at 10:33:50AM -0800, Prasad Singamsetty wrote:
On 11/29/2017 7:25 PM, Peter Xu wrote:
On Wed, Nov 29, 2017 at 01:05:22PM -0800, Prasad Singamsetty wrote:
Thanks Michael. Some comments below.
On 11/28/2017 9:32 AM
Thanks Michael. Some comments below.
On 11/28/2017 9:32 AM, Michael S. Tsirkin wrote:
On Tue, Nov 14, 2017 at 06:13:50PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
iova address width. This patch
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
iova address width. This patch provides a new parameter (x-aw-bits)
for intel-iommu to extend its address width to 48 bits but keeping the
default the same (39 bits). The reason for not changing the
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
host/iova address width so number of macros use hard coded values based
on that. This patch is to redefine them so they can be used with
variable address widths. This patch doesn't add an
From: Prasad Singamsetty
This pair of patches extends the intel-iommu to support address
width to 48 bits. This is required to support qemu guest with large
memory (>=1TB).
Patch1 implements changes to redefine macros and usage to
allow further changes to add support for 48 bit address wi
On 10/22/2017 11:37 PM, Peter Xu wrote:
On Fri, Oct 20, 2017 at 03:54:21PM -0700, Prasad Singamsetty wrote:
On 10/18/2017 8:33 PM, Peter Xu wrote:
On Wed, Oct 18, 2017 at 10:19:31AM -0700, Prasad Singamsetty wrote:
On 10/16/2017 8:56 PM, Peter Xu wrote:
On Mon, Oct 16, 2017 at 10:02
On 10/18/2017 8:33 PM, Peter Xu wrote:
On Wed, Oct 18, 2017 at 10:19:31AM -0700, Prasad Singamsetty wrote:
On 10/16/2017 8:56 PM, Peter Xu wrote:
On Mon, Oct 16, 2017 at 10:02:25AM -0700, Prasad Singamsetty wrote:
On 10/14/2017 8:53 PM, Peter Xu wrote:
On Fri, Oct 13, 2017 at 11:14
On 10/16/2017 8:56 PM, Peter Xu wrote:
On Mon, Oct 16, 2017 at 10:02:25AM -0700, Prasad Singamsetty wrote:
On 10/14/2017 8:53 PM, Peter Xu wrote:
On Fri, Oct 13, 2017 at 11:14:03AM -0600, Alex Williamson wrote:
On Fri, 13 Oct 2017 18:01:44 +0100
"Dr. David Alan Gilbert" wrote:
On 10/13/2017 10:14 AM, Alex Williamson wrote:
On Fri, 13 Oct 2017 18:01:44 +0100
"Dr. David Alan Gilbert" wrote:
* Prasad Singamsetty (prasad.singamse...@oracle.com) wrote:
Hi,
I am new to the alias. I have some questions on this subject
and seek some clarifications from the
On 10/14/2017 8:53 PM, Peter Xu wrote:
On Fri, Oct 13, 2017 at 11:14:03AM -0600, Alex Williamson wrote:
On Fri, 13 Oct 2017 18:01:44 +0100
"Dr. David Alan Gilbert" wrote:
* Prasad Singamsetty (prasad.singamse...@oracle.com) wrote:
Hi,
I am new to the alias. I have some questio
On 10/13/2017 10:01 AM, Dr. David Alan Gilbert wrote:
* Prasad Singamsetty (prasad.singamse...@oracle.com) wrote:
Hi,
I am new to the alias. I have some questions on this subject
and seek some clarifications from the experts in the team.
I ran into a couple of issues when I tried with large
Hi,
I am new to the alias. I have some questions on this subject
and seek some clarifications from the experts in the team.
I ran into a couple of issues when I tried with large configuration
( >= 1TB memory, > 255 CPUs) for x86_64 guest machine.
1. QEMU uses the default value of 40 (TCG_PHYS_AD
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