[Qemu-devel] [QUESTION] Licence for xilinx device emulation

source/documentation wich are Xilinx property). By the way where is the correct place to put this drivers ? I added it in hw/ppc but maybe there is a better location. Thanks for your advice. Pierre Mallard

[Qemu-devel] [PATCH v2 1/2] target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64

This patch remove limitation for fc[tf]id[*] on 32 bits targets and add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64 Signed-off-by: Pierre Mallard --- target-ppc/cpu.h|5 - target-ppc/fpu_helper.c |6 -- target-ppc/helper.h |2

[Qemu-devel] [PATCH v2 2/2] target-ppc : Add new processor type 440x5wDFPU

This patch add a new processor type 440x5wDFPU for Virtex 5 PPC440 with an external APU FPU in double precision mode Signed-off-by: Pierre Mallard --- target-ppc/cpu-models.c |3 +++ target-ppc/translate_init.c | 38 ++ 2 files changed, 41

[Qemu-devel] [PATCH v2 0/2] Enabling floating point instruction to 440x5 CPUs

This patch series enable floating point instruction in 440x5 CPUs which have the capabilities to have optional APU FPU in double precision mode. 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag 2) Create a new 440x5 implementing floating point instructions Pierre Mallard

Re: [Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs

No problem I repost, I triple check, hope this time everythng will be correct, sorry for the extra work time ... Pierre On Fri, Sep 12, 2014 at 4:29 PM, Tom Musta wrote: > On 9/11/2014 2:17 PM, Pierre Mallard wrote: > > This patch series enable floating point instruction in 440x5 CPUs

[Qemu-devel] [PATCH 1/2] target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64

This patch remove limitation for fc[tf]id[*] on 32 bits targets and add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64 --- target-ppc/cpu.h|5 - target-ppc/fpu_helper.c |6 -- target-ppc/helper.h |4 +--- target-ppc/translate.c |

[Qemu-devel] [PATCH 2/2] target-ppc : Add new processor type 440x5wDFPU

This patch add a new processor type 440x5wDFPU for Virtex 5 PPC440 with an external APU FPU in double precision mode --- target-ppc/cpu-models.c |3 +++ target-ppc/translate_init.c | 38 ++ 2 files changed, 41 insertions(+) diff --git a/target-ppc/cpu

[Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs

This patch series enable floating point instruction in 440x5 CPUs which have the capabilities to have optional APU FPU in double precision mode. 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag 2) Create a new 440x5 implementing floating point instructions Pierre Mallard

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta wrote: > > (1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer > Conversion instructions. > There is also fcfids and fcfidus which leads to 8 instructions (fcfid, fcfids, fcfidu, fcfidus and fctid, fctidz, fctidu, fctiduz), is this r

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

ms ok since it shall result in looking those that defined the PPC_64B flag. Will repost a patch in a few days taking in account your comments. Pierre On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta wrote: > On 9/10/2014 4:20 AM, Alexander Graf wrote: > > > > > > On 10.09.14 0

[Qemu-devel] [PATCH 1/3] target-ppc : Add floating point ability to 440x5 PPC CPU

This patch add some floating point operation for PPC440x5. Compile with PPC440x5_HAVE_FPU enabled in configure extra-cflags Signed-off-by: Pierre Mallard --- target-ppc/translate_init.c |4 1 file changed, 4 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc

[Qemu-devel] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type

together at the moment) Signed-off-by: Pierre Mallard --- target-ppc/cpu.h|7 +-- target-ppc/translate_init.c |2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b64c652..b5b3912 100644 --- a/target-ppc/cpu.h +++ b

[Qemu-devel] [PATCH 3/3] target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and remove their TARGET_PPC64 restriction

Apply the new PPC_FLOAT_64 flag to fctid[z] and fcfid. May also be applyed to fctidu[z] and fcfid[su][z], but since they are not mentionned in xilinx documentation it might not be needed yet. Signed-off-by: Pierre Mallard --- target-ppc/fpu_helper.c |7 +++ target-ppc/helper.h

[Qemu-devel] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

(fcfid, fctid, fctidz) 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 restrictions *** BLURB HERE *** Pierre Mallard (3): target-ppc : Add floating point ability to 440x5 PPC CPU target-ppc : Add PPC_FLOAT_64 flag to instructions type target-ppc : Add PPC_FLOAT_64 type to

[Qemu-devel] Address space per CPU at machine initialization time

Hi, I would like to instantiate two CPU on a XILINX board (FX100T). These two CPU shall have their own memory device (one DDR ram and one internal "xpr" RAM each) with addresses overlapping (0 to 0x each). Here is a snapshot of machine initialization routine working with one CPU : memory

[Qemu-devel] [PATCH] target-ppc : Make hreg_store_msr returns exception

exception number, and helper_store_msr test for POWERPC_EXCP_NONE. Signed-off-by: Pierre Mallard --- target-ppc/excp_helper.c |2 +- target-ppc/helper_regs.h |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index