On 5/28/25 12:49, Manos Pitsidianakis wrote:
It's not too large, overall.
#[repr(C)]
-#[derive(qemu_api_macros::Object)]
+#[derive(qemu_api_macros::Object, qemu_api_macros::DeviceProperties)]
Is there more to be derived that is useful for Devices? Maybe the
macro can be DeviceState or Devic
-0,0 +1,273 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +
> > +//! Error class for QEMU Rust code
> > +//!
> > +//! @author Paolo Bonzini
> > +
> > +use std::{
> > +borrow::Cow,
> > +ffi::{c_char, c_int, c_void, CStr},
&g
On 1/13/25 09:04, Xiaoyao Li wrote:
On 12/17/2024 8:39 PM, Xiaoyao Li wrote:
This series grabs two patches related to feature_word_description() from
two different old threads, they are simple and straightforward.
Patch 1 is grabbed from [1] while patch 2 is grabbed from [2].
Ping...
Applie
Il ven 9 mag 2025, 09:58 Daniel P. Berrangé ha
scritto:
> On Fri, May 09, 2025 at 07:48:57AM +0200, Markus Armbruster wrote:
> > Nabih Estefan writes:
> >
> > > From: Peter Foley
> > >
> > > e.g.
> > > I 2025-02-28 09:51:05.240071-0800 624 stream.go:47
> qemu: Uninitialized value
n the test jobs.
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst | 2 ++
.gitlab-ci.d/buildtest-template.yml | 3 ++-
.gitlab-ci.d/buildtest.yml | 11 +++
rust/qemu-api/meson.build | 9 +
4 files changed, 16 insertions(+), 9 deletions(-)
di
On 5/26/25 16:20, Philippe Mathieu-Daudé wrote:
On 26/5/25 15:18, BALATON Zoltan wrote:
On Mon, 26 May 2025, Philippe Mathieu-Daudé wrote:
Only add default devices checking defaults_enabled().
Remove the unused usb_disabled field in MachineState.
At least for Mac machines this may be more com
On 5/26/25 16:20, Philippe Mathieu-Daudé wrote:
On 26/5/25 15:18, BALATON Zoltan wrote:
On Mon, 26 May 2025, Philippe Mathieu-Daudé wrote:
Only add default devices checking defaults_enabled().
Remove the unused usb_disabled field in MachineState.
At least for Mac machines this may be more com
o the same dependencies that C targets use: link_with for
libqemuutil, and objects for everything else.
Reported-by: Bernhard Beschow
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst | 2 --
rust/meson.build | 2 ++
rust/qemu-api/meson.build | 24 +++-
3 files
Queued, thanks.
Paolo
e.
Signed-off-by: Paolo Bonzini
---
configure | 8
python/scripts/vendor.py | 4 ++--
python/wheels/meson-1.5.0-py3-none-any.whl | Bin 959846 -> 0 bytes
python/wheels/meson-1.8.1-py3-none-any.whl | Bin 0 -> 1013001 bytes
This is not needed anymore now that tests link with libqemuutil.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/cell.rs | 22 +-
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/rust/qemu-api/src/cell.rs b/rust/qemu-api/src/cell.rs
index 05ce09f6cb6
rustdoc is effectively a custom version of rustc, and it is necessary to
specify it in order to run doctests from Meson. Add the relevant configure
option and environment variables.
Signed-off-by: Paolo Bonzini
---
configure | 8
meson.build
rly useful anyway
because all dependencies are converted by hand into Meson subprojects.
rustfmt is still not supported.
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst | 10 +++---
meson.build | 2 +-
rust/clippy.toml => clippy.toml | 0
ru
g the qemu-api crate
(which may help splitting the crate, too).
Note that this does *not* yet require 1.8.1 for all of QEMU; the
requirement is only there if Rust is enabled.
Paolo
Supersedes: <20250405100603.253421-1-pbonz...@redhat.com>
Paolo Bonzini (6):
meson: update to version 1
On 5/8/25 21:57, Babu Moger wrote:
Following changes are implemented in this series.
1. Fixed the cache(L2,L3) property details in all the EPYC models.
2. Add RAS feature bits (SUCCOR, McaOverflowRecov) on all EPYC models
3. Add missing SVM feature bits required for nested guests on all EPYC mo
On 5/27/25 15:42, Markus Armbruster wrote:
Paolo Bonzini writes:
Rust makes the current file available as a statically-allocated string,
but without a NUL terminator. Allow this by storing an optional maximum
length in the Error.
Note that for portability I am not relying on fprintf&#
On Tue, May 27, 2025 at 5:01 AM Akihiko Odaki wrote:
> I'd like to submit it with "[PATCH v4 05/11] qemu-thread: Avoid futex
> abstraction for non-Linux" because it aligns the implementations of
> Linux and non-Linux versions to rely on a store-release of EV_SET in
> qemu_event_set().
Ok, I see w
On 5/27/25 11:45, Zhao Liu wrote:
On Mon, May 26, 2025 at 04:24:45PM +0200, Paolo Bonzini wrote:
Date: Mon, 26 May 2025 16:24:45 +0200
From: Paolo Bonzini
Subject: [PATCH 02/12] subprojects: add the anyhow crate
X-Mailer: git-send-email 2.49.0
This is a standard replacement for Box which is
On 5/26/25 07:29, Akihiko Odaki wrote:
Changes in v4:
- Added patch "qemu-thread: Remove qatomic_read() in qemu_event_set()".
Hi Akihiko,
I'm not so confident about putting this patch before the other changes;
I'm referring basically to this hunk:
diff --git a/util/event.c b/util/event.c
inde
On 5/8/25 16:59, Xiaoyao Li wrote:
This is the v9 series of TDX QEMU enabling. The series is also available
at github:
https://github.com/intel-staging/qemu-tdx/tree/tdx-qemu-upstream-v9
Note, this series has a dependency on
https://lore.kernel.org/qemu-devel/20241217123932.948789-1-xiaoyao...@i
Queued, thanks.
Paolo
inted.
Signed-off-by: Paolo Bonzini
---
include/qapi/error-internal.h | 1 +
util/error.c | 8 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/qapi/error-internal.h b/include/qapi/error-internal.h
index d5c3904adec..6178ce4a63d 100644
--- a/include/qapi/
This is used to preserve the file and line in a roundtrip from
C Error to Rust and back to C.
Signed-off-by: Paolo Bonzini
---
include/qapi/error-internal.h | 26 ++
rust/wrapper.h| 1 +
util/error.c | 10 +-
3 files changed, 28
Do not silently adjust num_timers, and fail if intcap is 0.
Signed-off-by: Paolo Bonzini
---
hw/timer/hpet.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index d1b7bc52b7b..d78aba04bcd 100644
--- a/hw/timer/hpet.c
+++ b/hw
to a Rust Option using
unsafe { Optionfrom_foreign(c_error) }
Signed-off-by: Paolo Bonzini
---
subprojects/.gitignore| 1 +
subprojects/foreign-0.2-rs.wrap | 7 +
.../packagefiles/foreign-0.2-rs/meson.build | 26 +++
3 files
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 5 +++--
rust/hw/timer/hpet/src/hpet.rs | 5 +++--
rust/qemu-api/src/qdev.rs| 10 ++
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src
Provide an implementation of std::error::Error that bridges the Rust
anyhow::Error and std::panic::Location types with QEMU's Error*.
It also has several utility methods, analogous to error_propagate(),
that convert a Result into a return value + Error** pair.
Signed-off-by: Paolo Bo
Match the code in hpet.c; this also allows removing the
BqlCell from the num_timers field.
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/fw_cfg.rs | 7 +++
rust/hw/timer/hpet/src/hpet.rs | 16 +++-
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a
wrapper.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250520152750.2542612-4-zhao1@intel.com
[Remove .into() as well. - Paolo]
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/hpet.rs | 27 +++
1 file changed, 11 insertions(+), 16 deletions
The function name is not available in Rust, so make it optional.
Signed-off-by: Paolo Bonzini
---
util/error.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/util/error.c b/util/error.c
index 6c1033eaba5..b977007faaf 100644
--- a/util/error.c
+++ b/util/error.c
version 1, which QEMU has not been producing for
~15 years.
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/hpet.rs | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs
index
This is a standard replacement for Box which is more efficient (it
only
occcupies one word) and provides a backtrace of the error. This could be
plumbed
into &error_abort in the future.
Signed-off-by: Paolo Bonzini
---
rust/meson.build | 2 ++
subproj
oject is missing and
cannot be downloaded).
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/meson.build | 12 +++-
rust/meson.build | 16
rust/qemu-api-macros/meson.build | 14 +++---
rust/qemu-api/meson.build| 4 +---
4 files changed,
at https://www.qemu.org/docs/master/devel/rust.html but just
to be clear, there are no stupid questions, only stupid answers. :)
Paolo
Paolo Bonzini (12):
rust: make declaration of dependent crates more consistent
subprojects: add the anyhow crate
subprojects: add the foreign crate
util/err
On 9/27/24 22:26, Paolo Bonzini wrote:
On Fri, Sep 27, 2024 at 9:36 PM Stefan Hajnoczi wrote:
On Mon, 1 Jul 2024 at 11:02, Paolo Bonzini wrote:
+/// A type for which there is a canonical representation as a C datum.
+pub trait CloneToForeign {
+/// The representation of `Self` as a C
On 5/23/25 21:57, oltolm wrote:
The build failed when run on Windows. I replaced calls to Unix programs
like `cat` and `true` with calls to `python`. I wrapped calls to
`os.path.relpath` in try-except because it can fail when the two paths
are on different drives. I made sure to convert the Windo
Il gio 22 mag 2025, 10:12 Manos Pitsidianakis <
manos.pitsidiana...@linaro.org> ha scritto:
> This is unnecessary though, because once we have the
> const_refs_to_static feature we can introduce a QdevProp trait that
> returns a reference to a type's qdev_prop_* global variable. We cannot
> do thi
Il mer 21 mag 2025, 10:37 Paolo Bonzini ha scritto:
> > So... not sure what to do there. It seems like vm-memory is very close
> to
>
>> > being usable by QEMU, but maybe not completely. :(
>>
>> Is it possible or necessary for vm-memory to support overlap
Il mer 21 mag 2025, 11:22 Manos Pitsidianakis <
manos.pitsidiana...@linaro.org> ha scritto:
> Perhaps it'd be simpler to contribute const-ability to upstream bilge?
> Is From/Into the only problem trait?
Probably.
I was thinking we can generate
> from/into associated methods for each type that
Il mer 21 mag 2025, 13:12 Manos Pitsidianakis <
manos.pitsidiana...@linaro.org> ha scritto:
> On Wed, May 21, 2025 at 12:50 PM Alex
> > > -_reserved_unpredictable: u4,
> > > +#[bits(4)]
> > > +_reserved_unpredictable: u8,
> >
> > This does come off as a little janky - effectively casti
Il mer 21 mag 2025, 11:35 Manos Pitsidianakis <
manos.pitsidiana...@linaro.org> ha scritto:
> vm-memory is a very rigid API unfortunately. It's excellent for
> rust-vmm purposes. I presume it's possible to figure out a clever
> solution to satisfy both rust-vmm and QEMU use needs but I'm not sure
Il mer 21 mag 2025, 10:21 Zhao Liu ha scritto:
> I also realize that once FlatRange/FlatView is associated with
> GuestMemoryRegion/
> GuestMemory, it changes the usual practice in QEMU, where most memory
> operations
> are built around MemoryRegion/AddressSpace.
>
That shouldn't be a problem. I
; but anyway, I want to switch
to 1.83 for QEMU as well due to improved "const" support in the compiler.
Signed-off-by: Paolo Bonzini
---
rust/Cargo.toml | 1 +
rust/hw/char/pl011/Cargo.toml | 3 +-
rust/hw/char/pl011/meson.build | 11 +--
rust/hw/char
tilities.
Together, these basically make the manual work go away.
Signed-off-by: Paolo Bonzini
---
rust/meson.build | 3 ++
subprojects/.gitignore| 1 +
subprojects/bitfield-struct-0.9-rs.wrap | 7
.../bitfield-struct-0.9-r
ke
bits!(Interrupt: E | MS | RT | TX | RX)
and expands it 1) add "Interrupt::" in front of all identifiers 2) convert
operators to the wordy const functions like "union". It supports boolean
operators "&", "|", "^", "!" and pa
This avoids the repeated ".0" when using the Interrupt struct.
Signed-off-by: Paolo Bonzini
---
rust/Cargo.lock | 1 +
rust/hw/char/pl011/Cargo.toml | 1 +
rust/hw/char/pl011/meson.build | 1 +
rust/hw/char/pl011/src/device.
These const functions make it possible to use enums easily together
with the bitfield-struct crate.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api-macros/src/lib.rs | 48 ++---
1 file changed, 38 insertions(+), 10 deletions(-)
diff --git a/rust/qemu-api-macros/src
like "bilge" and I think it's usage of arbitrary-width
types like "u4" is very nice and readable. If it ever grows "const"
capabilities it's certainly possible to come back to it, but right
now I feel that the trade-off leans towards the switch.
Paolo
Pa
Signed-off-by: Paolo Bonzini
---
rust/Cargo.lock | 71 ++---
rust/qemu-api/src/vmstate.rs| 34 ++
subprojects/.gitignore | 7 --
subprojects/arbitrary-int-1-rs.wrap | 10 ---
subprojects/bilge-0.2
Il mar 20 mag 2025, 21:01 Stefan Hajnoczi ha scritto:
> On Mon, May 19, 2025 at 2:52 PM Tanish Desai
> wrote:
> >
> > Remove hot paths from .c file and added it in .h file to keep it inline.
>
> Please include performance results in the commit description so it's
> clear what impact this change
On 5/20/25 18:23, Zhao Liu wrote:
HPET does some very simple memory accesses; a good safe solution
for this may be the ``vm-memory`` crate. While I have not looked into
using it, ``vm-memory`` and ``vm-virtio`` were written with QEMU's
use cases in mind.
I'm working on this and trying to wrap s
On 5/20/25 17:27, Zhao Liu wrote:
Currently, HPET adjusts num_timers in hpet_realize(), and doesn't change
it in any other place. And this field is initialized as a property.
Properties are initialized *after* hpet_init. For hw/timer/hpet you can
check s->num_timers and return an error if it'
On Tue, May 20, 2025 at 1:33 PM Daniel Henrique Barboza
wrote:
> > In general a lot (if not all) of the profile code should be moved out
> > of tcg-cpu.c and into riscv_cpu_class_base_init(). I didn't do that
> > because I didn't want to balloon an already-large series, but it's a
> > pretty obvi
On 5/20/25 14:51, Kohei Tokunaga wrote:
target_kconfig = []
foreach sym: accelerators
-# Disallow 64-bit on 32-bit emulation and virtualization
-if host_long_bits < config_target['TARGET_LONG_BITS'].to_int()
- continue
+if host_arch != 'wasm32'
+ # Disallow 64-bit on
On 5/20/25 13:30, Magnus Kulke wrote:
Write CPU register state to MSHV vCPUs. Various mapping functions to
prepare the payload for the HV call have been implemented.
Signed-off-by: Magnus Kulke
---
include/system/mshv.h | 41 ++
target/i386/mshv/mshv-cpu.c | 249 ++
On 5/20/25 13:50, Daniel P. Berrangé wrote:
+if get_option('mshv').allowed() and host_os == 'linux'
+ if get_option('mshv').enabled() and host_machine.cpu() != 'x86_64'
+error('mshv accelerator requires x64_64 host')
+ endif
+ accelerators += 'CONFIG_MSHV'
This enables MSHV for non-x86 w
On 5/20/25 13:29, Magnus Kulke wrote:
Hello all,
as previously announced here, we are working on an integration that will
expose the HyperV hypervisor to QEMU on Linux hosts. HyperV is a Type 1
hypervisor with a layered architecture that features a "root partition"
alongside VMs as "child partit
On 5/20/25 13:29, Magnus Kulke wrote:
Introduce headers for the Microsoft Hypervisor (MSHV) userspace ABI,
including IOCTLs and structures used to interface with the hypervisor.
These definitions are based on the upstream Linux MSHV interface and
will be used by the MSHV accelerator backend in l
On 5/20/25 13:30, Magnus Kulke wrote:
diff --git a/include/system/mshv.h b/include/system/mshv.h
index c7ee4f0cc1..4c1e901835 100644
--- a/include/system/mshv.h
+++ b/include/system/mshv.h
@@ -40,6 +40,10 @@
*/
#define MSHV_USE_IOEVENTFD 1
+#define MSHV_USE_KERNEL_GSI_IRQFD 1
Please mak
On 5/20/25 13:30, Magnus Kulke wrote:
+static void populate_special_regs(const hv_register_assoc *assocs,
+ X86CPU *x86cpu)
+{
+CPUX86State *env = &x86cpu->env;
+
+populate_segment_reg(&assocs[0].value.segment, &env->segs[R_CS]);
+populate_segment_reg(
These:
+/* Defines poached from apicdef.h kernel header. */
+static u_int32_t APIC_MODE_NMI = 0x4;
+static u_int32_t APIC_MODE_EXTINT = 0x7;
are available in other QEMU headers (search for APIC_DM_NMI,
APIC_DM_EXTINT).
Also they should have been #defines rather than statics; and also these
On 5/20/25 13:29, Magnus Kulke wrote:
+/* cpu */
+/* EFER (technically not a register) bits */
+#define EFER_LMA ((uint64_t)0x400)
+#define EFER_LME ((uint64_t)0x100)
There's already MSR_EFER_LMA and MSR_EFER_LME, please use them.
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 4f
On 5/20/25 15:50, Paolo Bonzini wrote:
You need support in the hypervisor for this: KVM and HVF both have it.
There are two ways to do it
Sorry - I left out the other way which is to pass something *into*
MSHV_RUN_VP since only half of it is currently used (I think). But
that's
On 5/20/25 13:30, Magnus Kulke wrote:
Qemu maps regions of userland multiple times into the guest. The MSHV
kernel driver detects those overlapping regions and rejects those
mappings.
Can you explain what you see? QEMU doesn't do that, just look at KVM code:
static bool kvm_check_memslot_over
On 5/20/25 13:30, Magnus Kulke wrote:
+int ret;
+hv_message exit_msg = { 0 };
You probably don't want to fill 512 bytes on every vmentry. Maybe pass
&exit_msg up from mshv_cpu_exec()?
+/*
+ * Read cpu->exit_request before KVM_RUN reads run->immediate_exit.
+
"supported" can be computed on the fly based on the max_satp_mode.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu_cfg.h | 4 +---
target/riscv/cpu.c | 34 --
2 files changed, 25 insertions(+), 13 deletions(-)
di
Signed-off-by: Paolo Bonzini
---
hw/riscv/virt-acpi-build.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 1eef2fb4eb3..e693d529e15 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
On 5/20/25 13:30, Magnus Kulke wrote:
+static int emulate_instruction(CPUState *cpu,
+ const uint8_t *insn_bytes, size_t insn_len,
+ uint64_t gva, uint64_t gpa)
+{
+X86CPU *x86_cpu = X86_CPU(cpu);
+CPUX86State *env = &x86_cpu->en
On 5/19/25 14:07, Björn Töpel wrote:
When realizing the cpus, the first cpu calls riscv_cpu_add_profiles()
all profiles are disabled, whereas for the other cpu calls to
riscv_cpu_add_profiles() have some profiles enabled. Having some
profiles enabled, will issue a call to cpu_set_profile() that w
001_ECX]")
Reported-by: Ewan Hai
Signed-off-by: Xiaoyao Li
Link: https://lore.kernel.org/r/20250514031652.838763-2-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i3
On 5/20/25 13:29, Magnus Kulke wrote:
Introduce a new helper function to decode x86 instructions from a
raw instruction byte stream. MSHV delivers an instruction stream in a
buffer of the vm_exit message. It can be used to speed up MMIO
emulation, since instructions do not have to be fetched and
On 5/20/25 14:02, Daniel P. Berrangé wrote:
On Tue, May 20, 2025 at 01:29:59PM +0200, Magnus Kulke wrote:
Introduce the initial scaffold for the MSHV (Microsoft Hypervisor)
accelerator backend. This includes the basic directory structure and
stub implementations needed to integrate with QEMU's a
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 75 ++
1 file changed, 35 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 48939adaafe..000fcc6a1d6 100644
--- a/target/riscv
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 79 +++---
2 files changed, 37 insertions(+), 43 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index
They are used to provide the nice QOM properties for svNN,
but the canonical source of the CPU configuration is now
cpu->cfg.max_satp_mode. Store them in the ArchCPU struct.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 14 ++
target/ri
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 39 ---
1 file changed, 16 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 17ad8b2ca1f..689c33916e0 100644
--- a/target/riscv/cpu.c
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 74 --
2 files changed, 21 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index
@intel.com
Signed-off-by: Paolo Bonzini
---
qapi/misc-target.json | 12 ++--
hw/i386/sgx-stub.c| 4 ++--
hw/i386/sgx.c | 14 +++---
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/qapi/misc-target.json b/qapi/misc-target.json
index a1275d3873a..6b3c9d8bd58
In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int. Make the insertion_test
optional, too.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/th_csr.c | 13 -
1 file changed, 4 insertions(+), 9 deletions
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 80 +-
1 file changed, 23 insertions(+), 57 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 000fcc6a1d6..640aa958fd4 100644
--- a/target/riscv
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 61 +-
1 file changed, 28 insertions(+), 33 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 12f4bc41514..5d2ccf647dd 100644
--- a/target/riscv
-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
qapi/misc-target.json | 6 +++---
hw/i386/sgx.c | 18 +-
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/qapi/misc-target.json b/qapi/misc-target.json
index 42e4a7417dc..a1275d3873a 100644
--- a/qapi/misc
SGXEPCSection, delete the redundant word "info".
Reported-by: Markus Armbruster
Signed-off-by: Zhao Liu
Acked-by: Markus Armbruster
Link: https://lore.kernel.org/r/20250513143131.2008078-2-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
qapi/misc-target.json | 4 ++--
1 file chan
end of riscv_cpu_init().
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 640aa958fd4..629ac37501e 100644
--- a/target/riscv/cpu.c
+++ b/target
arent profile mechanism.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 85 +-
2 files changed, 48 insertions(+), 38 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
is
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 4
target/riscv/cpu.c | 42 +-
target/riscv/kvm/kvm-cpu.c | 6 ++
3 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d
ix their documentation to reflect this difference.
Reported-by: Markus Armbruster
Suggested-by: Paolo Bonzini
Signed-off-by: Zhao Liu
Acked-by: Markus Armbruster
Link: https://lore.kernel.org/r/20250513143131.2008078-3-zhao1....@intel.com
Signed-off-by: Paolo Bonzini
---
qapi/misc-target
: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 93 ++
2 files changed, 46 insertions(+), 48 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 29b01e9aa86..f3d70afb866 100644
--- a
o...@intel.com
Signed-off-by: Paolo Bonzini
---
target/i386/hvf/x86_cpuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c
index fa131b18c6d..0798a0cbafb 100644
--- a/target/i386/hvf/x86_cpuid.c
+++ b/target/i386/hvf
Almost all users of cpu->cfg.satp_mode care about the "max" value
satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM
properties back into it. For TCG, deduce the bitmap of supported modes
from valid_vm[].
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonz
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 58 ++
1 file changed, 17 insertions(+), 41 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 54fce767657..8b82a1b7b33 100644
--- a/target/riscv
rnel.org/r/20250429170354.150581-2-rakeshjb...@gmail.com
Signed-off-by: Paolo Bonzini
---
hw/pci-host/gt64120.c | 82 +--
1 file changed, 48 insertions(+), 34 deletions(-)
diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
index 56a6ef93b7a..b12a25696c4 100644
--
Start putting all the CPU definitions in a struct. Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 4
target/riscv/cpu.c | 27
Prepare for adding more fields to RISCVCPUDef and reading them in
riscv_cpu_init: instead of storing the misa_mxl_max field in
RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
and go through it.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/
t all, not yet at least.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d92874baa06..0f7ce5305be 100644
--- a/target/riscv/cpu.c
+++ b/target/
Since all TYPE_RISCV_CPU subclasses support a class_data of type
RISCVCPUDef, process it even before calling the .class_init function
for the subclasses.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 21 ++---
1 file changed, 10 insertions
From: Rakesh Jeyasingh
pci_host_data_be_ops became unused after endianness fixes
Suggested-by: Paolo Bonzini
Signed-off-by: Rakesh Jeyasingh
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Thomas Huth
Link: https://lore.kernel.org/r/20250429170354.150581-3-rakeshjb...@gmail.com
Signed-off-by
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 113 +
1 file changed, 31 insertions(+), 82 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8b82a1b7b33..2b26f23bd0a 100644
--- a/target/riscv
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 127 +
1 file changed, 60 insertions(+), 67 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5d2ccf647dd..48939adaafe 100644
--- a/target/riscv
The maximum available SATP mode implies all the shorter virtual address sizes.
Store it in RISCVCPUConfig and avoid recomputing it via satp_mode_max_from_map.
Reviewed-by: Alistair Francis
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 11
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