[Qemu-devel] How qemu performs CMOVcc instruction in target-i386/translate.c?

2015-05-11 Thread Pang Wing
Hi, I'm still trying to understanding how disas_insn in *target-i386/translate.c* works. Currently I met "*case 0x140 ... 0x14f: /* cmov Gv, Ev */*", I thought it just check the condition and execute the MOV according to the condition. However, in *gen_cmovcc1 *function, I have no idea where th

[Qemu-devel] How qemu access memory in target-i386/translate.c disas_insn function?

2015-02-11 Thread Pang Wing
Hi, I'm trying to understanding how disas_insn in target-i386/translate.c works. However, I'm confused at disas_insn function. In /* arith & logic */ part, when f == 0 (OP Ev, Gv) && mod != 3, I found these codes: gen_lea_modrm(env, s, modrm); opreg = OR_TMP0; gen_op_mov_v_reg(ot, cpu_T[1], re