Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property

commit e9f186e514a70557d695cadd2c2287ef97737023 > Author: Peter A. G. Crosthwaite > Date: Mon Mar 5 14:39:12 2012 +1000 > > cadence_gem: initial version of device model > > Device model for cadence gem ethernet controller. > > Signed-off-by: Peter A. G. Crosth

Re: [Qemu-devel] [PATCH] configure: For libgcrypt if pkg-config is available use it

On 5 January 2017 at 01:27, Daniel P. Berrange wrote: > On Thu, Jan 05, 2017 at 12:56:52AM +1000, Nathan Rossi wrote: >> If libgcrypt info is available with pkg-config use it over using the >> libgcrypt-config. pkg-config is preferred due to is compatibility with >> cross-c

[Qemu-devel] [PATCH] configure: For libgcrypt if pkg-config is available use it

, then falling back to use libgcrypt-config if available. This follows a similar process to how libsdl is handled. Signed-off-by: Nathan Rossi --- configure | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/configure b/configure index 218df87d21..6558121de8 100755

Re: [Qemu-devel] [PATCH] dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX

On Thu, Sep 22, 2016 at 6:40 AM, Alistair Francis wrote: > On Wed, Sep 21, 2016 at 11:09 AM, Nathan Rossi wrote: >> Whilst according to the Zynq TRM this device covers a register region of >> 0x000 - 0x120. The register region is also shared with XADCIF prefix >> registe

[Qemu-devel] [PATCH] dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX

xadc, id "" mmio f8007100/0020 Mapping with XLNX_ZYNQ_DEVCFG_R_MAX = 0x100 / 4: dev: xlnx.ps7-dev-cfg, id "" mmio f8007000/0100 dev: xlnx,zynq-xadc, id "" mmio 0000f8007100/0020 Signed-off-by: Nathan Rossi ---

Re: [Qemu-devel] [PATCH v1 3/3] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers

On Thu, Feb 4, 2016 at 10:34 AM, Alistair Francis wrote: > Signed-off-by: Alistair Francis Tested-by: Nathan Rossi > --- > > target-arm/helper.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index

Re: [Qemu-devel] [PATCH v1 2/3] target-arm: Add Some of the performance monitor registers

On Thu, Feb 4, 2016 at 10:34 AM, Alistair Francis wrote: > This patch adds the following registers including read and write functions: > PMSELR, PMSELR_EL0, PMXEVCNTR, PMXEVCNTR_EL0, PMXEVTYPER and PMXEVTYPER_EL0. > > Signed-off-by: Alistair Francis Tested-by: Nathan Rossi >

Re: [Qemu-devel] [PATCH v1 1/3] target-arm: Add the pmceid0 and pmceid1 registers

On Thu, Feb 4, 2016 at 10:34 AM, Alistair Francis wrote: > Signed-off-by: Alistair Francis Tested-by: Nathan Rossi > --- > > target-arm/cpu-qom.h | 2 ++ > target-arm/cpu.c | 2 ++ > target-arm/cpu64.c | 2 ++ > target-arm/helper.c | 8 > 4 file

Re: [Qemu-devel] [PATCH v2] hw/misc/zynq_slcr: Change CPU clock rate for Linux boots

On Mon, Sep 14, 2015 at 10:07 PM, Peter Maydell wrote: > On 13 September 2015 at 23:42, Peter Crosthwaite > wrote: >> On Sun, Sep 13, 2015 at 1:47 PM, Peter Maydell >> wrote: >>> On 13 September 2015 at 21:22, Peter Crosthwaite >>> wrote: There may be more changes worth making on is_linux

[Qemu-devel] [PATCH] arm: xlnx-zynqmp: Fix up GIC region size

The GIC in ZynqMP cover a 64K address space, however the actual registers are decoded within a 4K address space and mirrored at the 4K boundaries. This change fixes the defined size for these regions as it was set to 0x4000/16K incorrectly. Signed-off-by: Nathan Rossi --- include/hw/arm/xlnx

Re: [Qemu-devel] [PATCH qom v1 1/1] qom/object.c: Split out object and class caches.

; Developers; Andreas Färber; Nathan Rossi > Subject: Re: [Qemu-devel] [PATCH qom v1 1/1] qom/object.c: Split out > object and class caches. > > Hi > > On Wed, Dec 4, 2013 at 1:40 AM, Paolo Bonzini wrote: > > Il 28/11/2013 05:27, Peter Crosthwaite ha scritto: > >>