h
can in turn lead to page faults.
The fix is simple: add a special case for these instructions. It did not
fit cleanly into the existing case, so some cut-and-paste was necesary.
Signed-off-by: Nathan Froyd
---
target-i386/translate.c | 10 ++
1 file changed, 10 insertions(+)
diff --
On 05/23/2011 01:36 PM, Guan, Qiang wrote:
> I want to figure out what is happening in emulating the floating point
> calculation in QEMU. I checked the codes in target-i386/translate.c, but I
> cannot find anything about floating point calculation, I can only find the
> emulation about integer "mu
On Wed, Apr 20, 2011 at 01:04:48PM +0100, Peter Maydell wrote:
> I need to add ARM support for fused multiply-accumulate (vfma,vfms),
> so perhaps in the long run it would be better to make them softfloat
> primitives? (they are after all in the new IEEE spec, so they're in
> softfloat's domain in
On Tue, Apr 12, 2011 at 11:59:29PM +0200, Aurelien Jarno wrote:
> Given that float32_*() functions are IEEE754 compliant, the efscmp*()
> functions are correctly implemented, while efstst*() are not. This
> patch reverse the implementation of this two groups of functions and
> fix the comments. It
On Sun, Apr 10, 2011 at 09:13:05PM +0200, Aurelien Jarno wrote:
> SH4 is always using softfloat, so it's possible to have helpers directly
> taking float32 or float64 value. This allow to get rid of conversions
> through CPU_{Float,Double}U.
Eh, I think this punning on i32/f32 and i64/f64 values i
On Mon, Mar 28, 2011 at 03:15:08PM +0100, Peter Maydell wrote:
> On 14 March 2011 05:35, Nathan Froyd wrote:
> > Oh, right. I am ambivalent as to whether passing env to such functions
> > is the right thing to do or not.
>
> So did this amount to a request for a change t
On Sat, Mar 26, 2011 at 11:58:37AM +0500, Khansa Butt wrote:
> Subject: [PATCH] MIPS64 user mode emulation in QEMU
> This patch adds support for Cavium Network's
> Octeon 57XX user mode instructions. Octeon
> 57xx is based on MIPS64. So this patch is
> the first MIPS64 User Mode Emulation in
On Thu, Mar 24, 2011 at 04:58:46PM +0100, Alexander Graf wrote:
> We have successfully lazilized cc computation, so we need to manually
> trigger its calculation when gdb wants to fetch it. We also changed the
> variable name, so writing it writes into a different field now.
Wouldn't you want to:
On Wed, Mar 16, 2011 at 11:21:22AM +0100, Fabien Chouteau wrote:
> Signed-off-by: Fabien Chouteau
Reviewed-by: Nathan Froyd
-Nathan
On Mon, Mar 21, 2011 at 02:04:31PM +, Peter Maydell wrote:
> On 21 March 2011 13:48, Nathan Froyd wrote:
> > I like the direction this patch goes; you aren't by any chance going to
> > convert the passing/returning of float* to their appropriate int* types
> > to
e
> hand-rolled functions which were doing bitwise copies between the types
> via unions.
Reviewed-by: Nathan Froyd
I like the direction this patch goes; you aren't by any chance going to
convert the passing/returning of float* to their appropriate int* types
too, are you?
-Nathan
On Fri, Mar 11, 2011 at 10:31:31PM +, Peter Maydell wrote:
> On 11 March 2011 18:30, Nathan Froyd wrote:
> > Is there a reason that you don't simply use the global env rather than
> > passing in an extra parameter everywhere?
>
> Just following the pattern that gen
On Fri, Mar 11, 2011 at 06:12:20PM +, Peter Maydell wrote:
> Make the Neon helper routines use the correct FP status from
> the CPUEnv rather than using a dummy static one. This means
> they will correctly handle denormals and NaNs and will set
> FPSCR exception bits properly.
Is there a reaso
On Fri, Mar 11, 2011 at 06:12:21PM +, Peter Maydell wrote:
> Use the softfloat make_float32 and float32_val macros to convert between
> softfloat's float32 type and raw uint32_t types, rather than private
> conversion functions.
Reviewed-by: Nathan Froyd
-Nathan
On Fri, Mar 11, 2011 at 06:12:25PM +, Peter Maydell wrote:
> Add min and max operations to softfloat. This allows us to implement
> propagation of NaNs and handling of negative zero correctly (unlike
> the approach of having target helper routines return one of the operands
> based on the resul
On Thu, Mar 03, 2011 at 06:15:49PM +0200, Riku Voipio wrote:
> On Thu, Mar 03, 2011 at 07:46:27AM -0800, Nathan Froyd wrote:
> > On Thu, Mar 03, 2011 at 05:37:37PM +0200, Riku Voipio wrote:
> > > PTHREAD_STACK_MIN (16KB) is somewhat inadequate for a new stack. follow
> &
On Thu, Mar 03, 2011 at 05:37:37PM +0200, Riku Voipio wrote:
> PTHREAD_STACK_MIN (16KB) is somewhat inadequate for a new stack. follow
> the pthread_create defaults, ie setting to RLIMIT_STACK or if unlimited
> to 2MB.
For what sort oof cases is it inadequate? This stack is just for QEMU's
usage
On Fri, Feb 11, 2011 at 04:53:30PM +, Peter Maydell wrote:
> On 11 February 2011 16:14, Peter Maydell wrote:
> > +void HELPER(neon_unzip)(CPUState *env, uint32_t insn)
> > +{
> > + int rd = ((insn >> 18) & 0x10) | ((insn >> 12) & 0x0f);
> > + int rm = ((insn >> 1) & 0x10) | (insn & 0x0f)
On Fri, Feb 11, 2011 at 05:12:32PM +, Peter Maydell wrote:
> On 11 February 2011 17:03, Nathan Froyd wrote:
> > I do think the preferred way would be to extract rd, rm, size, and Q
> > up-front, rather than having the helper twiddle instruction bits.
>
> OK. You'
should be propagated instead of a new
> qNaN to be generated. Fix that by calling fload_invalid_op_excp()
> only for the exception generation (if enabled), and use the softfloat
> code to correctly compute the result.
>
> Cc: Alexander Graf
> Cc: Peter Maydell
> Cc: Nath
> instead.
>
> Cc: Alexander Graf
> Cc: Peter Maydell
> Cc: Nathan Froyd
> Signed-off-by: Aurelien Jarno
Reviewed-by: Nathan Froyd
-Nathan
On Tue, Jan 11, 2011 at 10:01:30PM +0100, Aurelien Jarno wrote:
> case "$target_arch2" in
> -
> alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
> +
> alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|m
On Thu, Jan 06, 2011 at 03:34:38PM +, Peter Maydell wrote:
> Similarly I'm dubious about uses in helper_fsel, helper_fcmpu
> and helper_fcmpo, efsctsi, efsctui, efsctsiz, efsctuiz, efsctsf,
> efsctuf and all the helper_efd* functions. I haven't actually
> checked them all, but for instance efdc
On Sun, Jan 02, 2011 at 01:06:49PM +0100, Aurelien Jarno wrote:
> Use the new function float32_is_any_nan() instead of
> float32_is_quiet_nan() || float32_is_signaling_nan().
>
> Cc: Alexander Graf
> Signed-off-by: Aurelien Jarno
Reviewed-by: Nathan Froyd
> @@ -1938,7 +1938
TARGET_POWERPC.
Reviewed-by: Nathan Froyd
> + * A signaling NaN is always quietened before returning it.
I think "silenced" is more natural here, but I can understand preferring
"quiet" in keeping with NaN terminology.
-Nathan
On Mon, Dec 20, 2010 at 10:17:50PM -0800, maheen butt wrote:
> hi I 'm working with fedora core 13(64 bit) x86_64 platform. I
> configured QEMU with --enable-nptl switch but I'm not able to run
> programs containing POSIX threads or fork system call. I run this
> commandqemu-x86_64 thread it gives
On Sat, Dec 18, 2010 at 10:39:05AM +, Peter Maydell wrote:
> On 18 December 2010 02:30, Nathan Froyd wrote:
> > So adding _t suffixes in appropriate places should be a no-op, except
> > for uint16/int16--and those types are never used.
>
> Eh? If you comment out the int1
On Fri, Dec 17, 2010 at 11:32:03PM +, Peter Maydell wrote:
> On 17 December 2010 17:54, Andreas Färber wrote:
> > My patch does not touch the bits* types. I didn't notice any problem there.
> >
> > I replaced int32 by int32_t, int64 by int64_t etc. No sane code puts more
> > than 32 bits into
of the low word.
>
> This fixes the issues reported in
> https://bugs.launchpad.net/qemu/+bug/670883
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
be special-cased.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
On Mon, Dec 06, 2010 at 05:00:07PM +, Peter Maydell wrote:
> Add functions float*_maybe_silence_nan() which ensure that a
> value is not a signaling NaN by turning it into a quiet NaN.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
On Mon, Dec 06, 2010 at 05:00:05PM +, Peter Maydell wrote:
> Add float*_is_any_nan() functions which return true if the argument
> is a NaN of any kind (quiet or signalling).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
On Mon, Dec 06, 2010 at 04:48:25PM +, Peter Maydell wrote:
> I'm not sure how well it would fit into being committed to qemu (yet):
> it works as a program where you run half of it on real ARM hardware
> and the other half under qemu (or valgrind) and it compares register
> results after execut
On Thu, Nov 11, 2010 at 06:23:55PM +, Peter Maydell wrote:
> Correct the decoding of source and destination registers
> for the VFP forms of the VCVT instructions which convert
> between floating point and integer or fixed-point.
>
> Signed-off-by: Peter Maydell
Reviewed-b
t; This change was produced by:
> perl -p -i -e 's/_is_nan/_is_quiet_nan/g' $(git grep -l is_nan)
> (with the results manually checked.)
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
Thank you for doing this.
-Nathan
On Wed, Dec 01, 2010 at 09:52:13AM -0800, Richard Henderson wrote:
> I think I've lost the thread a bit -- is the proposal to
> replace the existing float*_is_nan with _is_quiet_nan and
> invent a new function that returns true for both Q+S? That
> at least would be monotonic improvement for Alpha
On Tue, Nov 30, 2010 at 11:15:56AM +, Peter Maydell wrote:
> On 29 November 2010 19:54, Nathan Froyd wrote:
> > Yes, this is ugly. Are you up for running:
> >
> > perl -p -i -e 's/float(\d+)_is_nan/float\1_is_quiet_nan/g' target-*/*.c
> >
> > (
On Mon, Nov 29, 2010 at 08:04:42PM +, Peter Maydell wrote:
> On 29 November 2010 19:54, Nathan Froyd wrote:
> > On Mon, Nov 29, 2010 at 07:25:18PM +, Peter Maydell wrote:
> >> (b) add to and extend the softfloat API whenever you have some
> >> floating-poi
On Mon, Nov 29, 2010 at 07:25:18PM +, Peter Maydell wrote:
> On 29 November 2010 17:49, Nathan Froyd wrote:
> > On Tue, Nov 23, 2010 at 06:53:47PM +, Peter Maydell wrote:
> > As with other NaN-handling patches, I don't think the bit-twiddling here
> > is a
m to deliberately modify the state via the ucontext structure.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
m to deliberately modify the state via the ucontext structure.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
g compatible with the older kernels, which don't save and
> restore VFP registers either.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
ux-user mode.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
rs to userspace signal handlers.)
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
l
Reviewed-by: Nathan Froyd
-Nathan
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
ngtsson
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
er Maydell
Reviewed-by: Nathan Froyd
-Nathan
was inverted
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
On Tue, Nov 23, 2010 at 06:53:47PM +, Peter Maydell wrote:
> The ARM ARM defines that if the input to a single<->double conversion
> is a NaN then the output is always forced to be a quiet NaN by setting
> the most significant bit of the fraction part.
>
> Signed-off-by: Peter Maydell
>
> @@
at least 16 bits wide (and so is usually 32 bits).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
On Mon, Nov 29, 2010 at 04:49:24PM +, Peter Maydell wrote:
> On 29 November 2010 16:38, Nathan Froyd wrote:
> > Why not just use:
> >
> > static int float32_is_any_nan(float32 x)
> > {
> > return float32_is_nan(x) || float32_is_signaling_nan(x);
> > }
&
On Tue, Nov 23, 2010 at 06:53:46PM +, Peter Maydell wrote:
> The ARM architecture mandates that converting a NaN value to
> integer gives zero (if Invalid Operation FP exceptions are
> not being trapped). This isn't the behaviour of the SoftFloat
> library, so NaNs must be special-cased.
>
> +
On Tue, Nov 23, 2010 at 06:53:45PM +, Peter Maydell wrote:
> Signed-off-by: Peter Maydell
Reviewed-by: Nathan Froyd
-Nathan
On Mon, Nov 29, 2010 at 02:58:57PM +0100, Alexander Graf wrote:
> > Nathan Froyd a écrit :
> >> I'm sorry, what are the "both talks" you refer to above? Are you
> >> proposing an additional talk alongside your (Frédéric's) existing talk?
> >
On Mon, Nov 29, 2010 at 08:34:28AM -0600, Anthony Liguori wrote:
> On 11/28/2010 04:56 AM, Alexander Graf wrote:
>> On 28.11.2010, at 01:17, Nathan Froyd wrote:
>>> We (CodeSourcery) are very interested in Windows host support. (We
>>> distribute QEMU with our commeric
On Sun, Nov 28, 2010 at 09:20:25AM +0100, Frédéric Pétrot wrote:
>IMHO someone from code sourcery would be great, as they (Paul Brooks in the
>older versions, it seems that Nathan is now taking over) are contributing
>most of the ARM emulation stuff.
Well, Paul still knows way more tha
On Fri, Nov 26, 2010 at 01:26:31AM +0100, François Revol wrote:
> >> the people we are addressing and we would like to bring together is from
> >> the QEMU emulation community.
> >> We are interested in running different ISAs mainly under Linux and Windows
> >> versions. There is a huge additiona
On Sat, Nov 27, 2010 at 11:26:05PM +0100, Alexander Graf wrote:
> On 27.11.2010, at 20:00, Peter Maydell wrote:
> > On 26 November 2010 16:34, wolfgang mueller wrote:
> >> In this case is it possible to do the introductionary talk of the workshop
> >> with a QEMU overview.
> >> People are here in
On Thu, Nov 11, 2010 at 06:23:58PM +, Peter Maydell wrote:
> The ARM architecture mandates that converting a NaN value to
> integer gives zero. This isn't the behaviour of the SoftFloat
> library, so NaNs must be special-cased.
This is correct, but it's really only correct if FP traps are disa
On Sat, Nov 06, 2010 at 07:24:39PM +0100, Torbjorn Granlund wrote:
> malc writes:
>
> ZF is undefined according to AMD's 24594.pdf page 69.
>
> Ah, you're right. It seems that all existing x86 implementations leave
> ZF alone, though. (I am not arguing that qeum is broken, the bug is in
>
major changes, we can comfortably run programs like the
above without exhausting memory. We do need to delete 'stack' from the
TaskState structure.
Signed-off-by: Nathan Froyd
---
linux-user/main.c|4 ++--
linux-user/qemu.h|2 --
linux-user/syscall.c | 11 +++
3
translation code accordingly.
Signed-off-by: Nathan Froyd
---
target-mips/helper.h|8
target-mips/op_helper.c | 28
target-mips/translate.c |8
3 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/target-mips/helper.h b
On Tue, Oct 19, 2010 at 09:57:13PM +0200, Lluís wrote:
> --- a/exec.c
> +++ b/exec.c
> @@ -688,6 +688,11 @@ static void page_flush_tb(void)
> }
> }
>
> +void tb_flush_jmp_cache (CPUState * env)
> +{
> +memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
> +}
> +
This is
On Mon, Aug 30, 2010 at 10:48:55AM -0500, Anthony Liguori wrote:
> No, this is GCC being stupid.
>
> How else do you terminate a list? IOW:
>
> MyDeviceInfo device_infos[] = {
> {"foo", 0, 2},
> {"bar", 0, 1},
> {} /* or { 0 } */
> };
>
> This is such a pervasive idiom that there's simply no
Your patch needs a Signed-off-by and preferably a From: as well.
** Tags added: powerpc
--
Incorrect translation of unary PPC/SPE instructions (efdneg etc.)
https://bugs.launchpad.net/bugs/617528
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed t
On Wed, Aug 18, 2010 at 12:15:09PM -0700, Peter W Schultz wrote:
> How would I go about modifying the qemu source to implement SWP
> atomically? I have been studying the source for a few days now, and I
> am at a loss as to what all needs to be done.
You should look at how the load/store-exclusive
On Fri, Jul 09, 2010 at 03:38:34PM +0900, Alexandre Courbot wrote:
> This series of patch adds support for the missing ldc & stc privileged
> instructions with the sgr register. In order to take the difference
> of support between SH4A and SH4 (which does not recognize ldc with sgr),
> the LDST mac
On Wed, Jun 09, 2010 at 04:10:25PM +0200, Aurelien Jarno wrote:
> On Tue, Jun 08, 2010 at 01:29:55PM -0700, Nathan Froyd wrote:
> > This patch series adds support for the microMIPS ASE. microMIPS is a
> > new ASE similar to MIPS16, but re-encodes the entire instruction set
> &g
Signed-off-by: Nathan Froyd
---
target-mips/translate_init.c | 61 ++
1 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index b79ed56..8e17f4b 100644
--- a/target-mips
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers. The ISA mode is selectable via a user-writable CP0.Config3
flag.
Signed-off-by: Nathan Froyd
---
target-mips/cpu.h|1 +
target-mips/helper.c | 21 +++--
2 files changed, 16 insertions
: Nathan Froyd
---
target-mips/translate.c | 24 +---
1 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8d532d5..2754b2e 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -68,6 +68,7
Add FMT_* constants for the floating-point format field in opcodes and
tweak a few places to use them. Add enums for various invocations of
FOP and tweak gen_farith and its lone caller accordingly.
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 437
Move all knowledge about coprocessor-checking and register numbering
into the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 164 +++
1 files changed, 81 insertions(+), 83 deletions(-)
diff --git a/target-mips
Signed-off-by: Nathan Froyd
---
hw/mips_mipssim.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index a747de5..293d99e 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -106,7 +106,10 @@ static void main_cpu_reset(void
Signed-off-by: Nathan Froyd
---
linux-user/main.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 0f23fc9..ad292f1 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3271,7 +3271,10 @@ int main(int argc, char
into separate patch
group patches more logically
changes from v1:
fix re-introduction of previously deleted code noted by rth
Nathan Froyd (8):
target-mips: define constants for magic numbers
target-mips: refactor c{,abs}.cond.fmt insns
target-mips: mips16 cleanups
target-mips
On Fri, Jun 04, 2010 at 11:35:45AM -0700, Richard Henderson wrote:
> On 05/24/2010 09:19 AM, Nathan Froyd wrote:
> > Signed-off-by: Nathan Froyd
> > ---
> > target-mips/translate_init.c | 61
> > ++
> > 1 files chang
On Fri, Jun 04, 2010 at 11:30:38AM -0700, Richard Henderson wrote:
> On 05/24/2010 09:19 AM, Nathan Froyd wrote:
> > +int (*ldfun)(target_ulong);
> > +
> > +switch (mem_idx)
> > +{
> > +case 0: ldfun = ldl_kernel; break;
> > +case 1: ldf
On Fri, Jun 04, 2010 at 10:45:32AM -0700, Richard Henderson wrote:
> On 05/24/2010 09:19 AM, Nathan Froyd wrote:
> > @@ -5937,8 +6031,8 @@ static void gen_farith (DisasContext *ctx, uint32_t
> > op1,
> > enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
> >
On Mon, May 24, 2010 at 09:19:34AM -0700, Nathan Froyd wrote:
> This patch series adds support for the microMIPS ASE. microMIPS is a
> new ASE similar to MIPS16, but re-encodes the entire instruction set
> into 16-bit and 32-bit instructions--in contrast to MIPS16, which
> re-encodes
Signed-off-by: Nathan Froyd
---
linux-user/main.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 18b52c0..76d443b 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3192,7 +3192,9 @@ int main(int argc, char **argv
Signed-off-by: Nathan Froyd
---
target-mips/translate_init.c | 61 ++
1 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index b79ed56..8e17f4b 100644
--- a/target-mips
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers.
Signed-off-by: Nathan Froyd
---
target-mips/helper.c | 21 +++--
1 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8102f03
Signed-off-by: Nathan Froyd
---
hw/mips_mipssim.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index a747de5..cd6c2be 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -106,7 +106,9 @@ static void main_cpu_reset(void
are identical to those for MIPS16; a given chip
cannot support both ASEs simultaneously.
changes from v1:
fix re-introduction of previously deleted code noted by rth
Nathan Froyd (10):
target-mips: break out [ls][wd]c1 and rdhwr insn generation
target-mips: add microMIPS-specific bits to
Move all knowledge about coprocessor-checking and register numbering
into the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 174 --
1 files changed, 91 insertions(+), 83 deletions(-)
diff --git a/target-mips
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 17 +
1 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 63844b8..cc445fb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -359,7
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 106 ++-
1 files changed, 59 insertions(+), 47 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c95ecb1..2075d09 100644
--- a/target-mips/translate.c
+++ b
Tweak gen_farith and its caller to use them.
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 266 ---
1 files changed, 180 insertions(+), 86 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2075d09..2568e16
There's a new ASE_MICROMIPS instruction flag, and some extra CP0_Config3
fields. The ISA and ISA_ON_EXC fields are specific to microMIPS. The
DSP2P is for version 2 of the DSP ASE.
Signed-off-by: Nathan Froyd
---
target-mips/cpu.h |3 +++
target-mips/mips-defs.h |1 +
2
On Thu, May 20, 2010 at 08:34:16AM -0700, Richard Henderson wrote:
> On 05/20/2010 07:52 AM, Nathan Froyd wrote:
> > +/* Tests */
> > +#define OP_COND(name, cond) \
> > +#defin
Tweak gen_farith and its caller to use them.
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 266 ---
1 files changed, 180 insertions(+), 86 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2075d09..2568e16
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers.
Signed-off-by: Nathan Froyd
---
target-mips/helper.c | 21 +++--
1 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8102f03
Move all knowledge about coprocessor-checking and register numbering
into the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 232 ++-
1 files changed, 149 insertions(+), 83 deletions(-)
diff --git a/target-mips
Signed-off-by: Nathan Froyd
---
linux-user/main.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 18b52c0..76d443b 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3192,7 +3192,9 @@ int main(int argc, char **argv
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 106 ++-
1 files changed, 59 insertions(+), 47 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c95ecb1..2075d09 100644
--- a/target-mips/translate.c
+++ b
Signed-off-by: Nathan Froyd
---
target-mips/translate.c | 17 +
1 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8a7f3e9..c42d8dd 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -359,7
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