Re: [PATCH v3] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

2023-06-23 Thread Narayana Murty N
On 5/23/23 15:45, Greg Kurz wrote: On Tue, 23 May 2023 12:20:17 +0530 Narayana Murty N wrote: On 5/22/23 23:50, Greg Kurz wrote: On Mon, 22 May 2023 12:02:42 -0400 Narayana Murty N wrote: Currently on PPC64 qemu always dumps the guest memory in Big Endian (BE) format even though the

[PATCH v4] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

2023-06-23 Thread Narayana Murty N
erNV) LE LE powernv(OPAL/PowerNV) BE LE pseries(OPAL/PowerNV/pSeries) KVMHV LE LE pseries TCG LE Fixes: 5609400a4228 ("target/ppc: Set the correct endianness for powernv memory dumps

Re: [PATCH v3] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

2023-05-24 Thread Narayana Murty N
On 5/23/23 15:52, Cédric Le Goater wrote: On 5/22/23 18:02, Narayana Murty N wrote: Currently on PPC64 qemu always dumps the guest memory in Big Endian (BE) format even though the guest running in Little Endian The patch is surely correct. I have problems understanding the config you are

Re: [PATCH v3] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

2023-05-22 Thread Narayana Murty N
On 5/22/23 23:50, Greg Kurz wrote: On Mon, 22 May 2023 12:02:42 -0400 Narayana Murty N wrote: Currently on PPC64 qemu always dumps the guest memory in Big Endian (BE) format even though the guest running in Little Endian (LE) mode. So crash tool fails to load the dump as illustrated below

[PATCH v3] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

2023-05-22 Thread Narayana Murty N
BE LE powernv LE KVM guest LE LE powernv BE KVM guest BE LE pseries KVM LE KVM guest LE LE pseries TCG LE guest LE Signed-off-by: Narayana Murty N

Re: [PATCH] target: ppc: Correctly initialize HILE in HID-0 for book3s processors

2023-05-15 Thread Narayana Murty N
On 5/15/23 12:02, Nicholas Piggin wrote: On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote: Vaibhav Jain writes: Hi Fabiano, Thanks for looking into this patch and apologies for the delayed reponse. Fabiano Rosas writes: Narayana Murty N writes: On PPC64 the HILE(Hypervisor

[PATCH v2] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

2023-05-09 Thread Narayana Murty N
|LE | BE| LE | ||---|----| Signed-off-by: Narayana Murty N --- Changes since V1: https://lore.kernel.org/qemu-devel/20230420145055.10196-1-nnmli...@linux.ibm.com/ The approach to solve the issue was changed based on feedback from Fabiano Rosas on patch V1. --- target/ppc/arch_dump.c | 2 +- 1 fi

Re: [PATCH] target: ppc: Correctly initialize HILE in HID-0 for book3s processors

2023-05-04 Thread Narayana Murty N
On 4/28/23 20:00, Fabiano Rosas wrote: Vaibhav Jain writes: Hi Fabiano, Thanks for looking into this patch and apologies for the delayed reponse. Fabiano Rosas writes: Narayana Murty N writes: On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0 register needs to be

[PATCH] target: ppc: Correctly initialize HILE in HID-0 for book3s processors

2023-04-20 Thread Narayana Murty N
wer8 : correcting "spr_register_hv" function parameter for initial value to HID0_ISA206_INIT_VAL in register_book3s_ids_sprs() References: 1. ISA 2.06, section 2.9 for POWER7,POWER8 2. ISA 3.0b, section 2.10 for POWER9 onwards - https://openpowerfoundation.org/specifications/