gdb/features/sparc/sparc64-fpu.xml;h=8710585774d821c660af5e76f92707637633daf7;hb=HEAD>
Thanks in advance
Mikael Szreder
On February 13, 2025 5:57:59 PM GMT+01:00, Richard Henderson
wrote:
>On 2/3/25 06:50, Mikael Szreder wrote:
>> The gdbstub implementation for the Sparc architecture w
Ping
On February 3, 2025 3:50:56 PM GMT+01:00, Mikael Szreder wrote:
>The gdbstub implementation for the Sparc architecture would incorectly
> calculate the the floating point register offset.
>This would cause register pairs(eg f32,f33) to point to the same value.
>
>Fixe
:
v2:
- Corrected a mistake I made in the FqTOx instruction
- Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions as well
Mikael Szreder (2):
target/sparc: Fix register selection for the fdtox and fqtox
instructions
target/sparc: Fix register selection for all F*TOx and FxTO
ves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder
---
target/sparc/insns.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 989c20b44a..694a28d88c 100644
--- a/target/sparc/in
Fixed a mistake I made in the FqTOx instruction.
Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions.
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder
---
ta
The gdbstub implementation for the Sparc architecture would incorectly
calculate the the floating point register offset.
This would cause register pairs(eg f32,f33) to point to the same value.
Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.")
Signed-off-
ves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder
---
target/sparc/insns.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 989c20b44a..694a28d88c 100644
--- a/target/sparc/in
