Re: [PATCH v4] riscv/gdbstub: add V bit to priv reg

On 15.12.2024 22:37, Yanfeng Liu wrote: This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit

Re: [PATCH v3] riscv/gdb: add V bit to priv register

Hi, apologies for the delayed review; I've just gotten to it now. On 06.12.2024 01:14, Yanfeng Liu wrote: This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc3. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for the value

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

Hi everyone, I'd like to chime in here because we are sitting on a similar patch which I wanted to send to the mailing list as soon as riscv-debug-spec v1.0.0 becomes ratified. For hypervisor support, `(qemu) info registers` isn't enough. We need to have both read and write access to the V-b