register generic read/write
functions to these power10 pmu sprs to fix it.
Signed-off-by: Madhavan Srinivasan
---
target/ppc/cpu.h | 6 ++
target/ppc/cpu_init.c | 34 ++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
On Monday 14 July 2014 02:45 PM, Bharat Bhushan wrote:
> Get trap instruction opcode from KVM and this opcode will
> be used for setting software breakpoint in following patch
>
> Signed-off-by: Bharat Bhushan
> ---
> v7->v8
> - No change
>
Reviewed By: Madhavan
-
> v7->v8
> - Decrement nip by 4 before calling ppc_cpu_do_interrupt()
>as pointed by "Madhavan Srinivasan"
Just a minor change. We increment the nip.
> - Also added missing cpu_sync()
>
> target-ppc/kvm.c | 93
>
On Thursday 10 July 2014 07:49 PM, Bharat Bhushan wrote:
> This patch allow insert/remove software breakpoint.
>
> When QEMU is not able to handle debug exception then we inject program
> exception to guest because for software breakpoint QEMU uses a ehpriv-1
> instruction;
> So there cannot be an
On Tuesday 24 June 2014 10:36 PM, bharat.bhus...@freescale.com wrote:
>
>
>> -Original Message-----
>> From: Madhavan Srinivasan [mailto:ma...@linux.vnet.ibm.com]
>> Sent: Tuesday, June 24, 2014 8:59 PM
>> To: Bhushan Bharat-R65777; ag...@suse.de
>>
On Tuesday 24 June 2014 05:40 PM, Bharat Bhushan wrote:
> This patch allow insert/remove software breakpoint
>
> Signed-off-by: Bharat Bhushan
> ---
> target-ppc/kvm.c | 71
> +---
> 1 file changed, 57 insertions(+), 14 deletions(-)
>
> diff
On Monday 16 June 2014 03:22 PM, bharat.bhus...@freescale.com wrote:
>
>
>> -Original Message-
>> From: qemu-ppc-bounces+bharat.bhushan=freescale@nongnu.org
>> [mailto:qemu-ppc-
>> bounces+bharat.bhushan=freescale@nongnu.org] On Behalf Of Madhavan
(in v2.01) and will generate an
Emulation assistance interrupt in hypervisor when executed.
KVM also has to be updated with this to make use of sw breakpoint.
Signed-off-by: Madhavan Srinivasan
---
target-ppc/kvm.c | 38 +++---
1 file changed, 35 insertions(+), 3
Hi team,
I am trying to understand the gdb breakpoint support in qemu. i could see
the arch_insert_sw_breakpoint adding a int3 opcode. But my question is,
when the break is hit, how it is propagated to gdb server. I mean which
routine or call is used from qemu to update the gdb server connected vi
