guest LIP status same
with the host.
Signed-off-by: Luwei Kang
Message-Id: <20201014080443.23751-2-luwei.k...@intel.com>
Signed-off-by: Eduardo Habkost
---
v1->v2:
Add a dependency on the Intel PT flag.
Test on SnowRidge Server(HW support LIP feature)：
1. "-cpu host"
guest.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 24
target/i386/cpu.h | 4
2 files changed, 28 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aeabdd5bd4..242ba8a870 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -672,6
guest LIP
status same with the host.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 29 +++--
target/i386/cpu.h | 4
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 24644abfd4..aeabdd5bd4 100644
--- a/target
4 and the CPUID values from leaf
0xe to 0x14 are all zero.
This patch moves the capabilities checking before setting the
level of the CPUID.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 63 ---
1 file changed, 32 insertions(+), 31 deletions(-)
e previous
submission(ddc2fc9).
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 90ffc5f..a0e39d1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6375,7 +6375,7 @@ s
f 0x14 and the
missing capabilities will cause some MSRs access failed.
This patch add a warning message to inform the user to extend
the CPUID level.
Suggested-by: Eduardo Habkost
Signed-off-by: Luwei Kang
---
v1->v2:
- Mask off Intel PT when the CPUID level < 0x14, not only a warnin
Add support for save/load PEBS baseline feature
IA32_PEBS_DATA_CFG MSR.
Signed-off-by: Luwei Kang
---
target/i386/cpu.h | 2 ++
target/i386/kvm.c | 14 ++
target/i386/machine.c | 24
3 files changed, 40 insertions(+)
diff --git a/target/i386/cpu.h
ts to
KVM guest when the KVM support PEBS virtualization and the "pebs" parameter
is true.
Signed-off-by: Luwei Kang
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 14 ++
target/i386/cpu.h | 7 +++
3 files changed, 22 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i3
PEBS feature virtualization required IA32_PEBS_ENABLE and
DS_AREA MSRs. This patch is to add the support of these MSRs
saved/loaded in guest.
Signed-off-by: Luwei Kang
---
target/i386/cpu.h | 6 ++
target/i386/kvm.c | 29 +
target/i386/machine.c | 25
The PEBS virtualization will be first supported on ICELAKE server.
This patchset introduce a new CPU parameter "pebs"(e.g.
"-cpu Icelake-Server,pmu=true,pebs=true") that use for enable PEBS
feature in KVM guest, and add the support for save/load PEBS MSRs.
Luwei Kang (3
tation and expose all the capabilities to guest.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 65 ---
1 file changed, 4 insertions(+), 61 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8c0d1e4..4d9e203 100644
--- a/t
est. As it will break the live migration safe, Intel PT will be
masked as unmigratable.
Luwei Kang (3):
i386: Remove the limitation of IP payloads for Intel PT
i386: Remove the CPUID limitation of Intel PT
i386: Mark the 'INTEL_PT' CPUID bit as unmigratable
payloads
have LIP values).
This patch will revert the previous limitation because the Intel new hardware
will set this bit and LIP == RIP for most/all real code.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/i386
After expose all the capabilities of Intel PT to KVM guest, the guest Intel
PT CPUID information may difference with same guest cpu model on differnt
hardware. It will block the live migration. This patch will mark the Intel
PT feature as unmigratable.
Signed-off-by: Luwei Kang
---
target/i386
capabilities will cause some MSRs access failed.
This patch add a warning message to inform the user to extend
the CPUID level.
Suggested-by: Eduardo Habkost
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/i386
capabilities will cause some MSRs access failed.
This patch add a warning message to inform the user to extend
the CPUID level.
Suggested-by: Eduardo Habkost
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/i386
This patch add a new feature words for IA32_PERF_CAPABILITIES (RO)
register that serve to expose PEBS output Intel PT feature.
The registers relate with PEBS need to be set/get when PEBS output
Intel PT is supported in guest.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 20
Intel processor introduce some hardware extensions that output PEBS record
to Intel PT buffer instead of DS area, so PEBS can be enabled in KVM guest
by PEBS output Intel PT. This patch adds a section for PEBS which use for
saves PEBS registers when the value is no-zero.
Signed-off-by: Luwei Kang
Intel Processor Trace required CPUID[0x14] but the cpuid_level
have no change when create a kvm guest with
e.g. "-cpu qemu64,+intel-pt".
Signed-off-by: Eduardo Habkost
Signed-off-by: Luwei Kang
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 9 +
target/i386/cpu.h | 3 ++
Intel Processor Trace required CPUID[0x14] but the cpuid_level
have no change when create a kvm guest with
e.g. "-cpu qemu64,+intel-pt".
Signed-off-by: Luwei Kang
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 9 +
target/i386/cpu.h | 3 +++
3 files changed, 13 insertion
Intel Processor Trace required CPUID[0x14] but the cpuid level
is 0xd when create a kvm guest with e.g. "-cpu qemu64,+intel-pt".
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
ind
[31] is set.
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ec1efd3a3c..3c0eda113e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -194,6 +194,8 @@
* bit[02]: Support
default value. Intel PT would be disabled
if any machine don't support this minial feature list.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
>From V3:
- fix some typo;
- add some comments and safty check.
---
target/i386/cp
From: Chao Peng
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.h | 22 ++
target/i386/kvm.c | 51
From: Chao Peng
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.h | 22 ++
target/i386/kvm.c | 51
default value. Intel PT would be disabled
If any machine don't support this minial feature list.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 53 +++--
target/i386/cpu.h | 1 +
target/i386/kvm.c
in diffrent hardware when this feature is enabled.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
v1->v2:
- In order to make this feature migration-safe, new feature word
information "FEAT_INTEL_PT_EBX" and "FEAT_INTEL_PT_ECX" be added.
Some constant value i
From: Chao Peng
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Luwei Kang
Signed-off-by: Chao Peng
---
target/i386/cpu.h | 22 ++
target/i386/kvm.c | 51
From: Chao Peng
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.h | 22 ++
target/i386/kvm.c | 51
From: Chao Peng
Expose Intel Processor Trace feature to guest.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 19 ++-
target/i386/cpu.h | 1 +
target/i386/kvm.c | 23 +++
3 files changed, 42 insertions(+), 1 deletion(-)
diff
From: Chao Peng
Expose Intel Processor Trace feature to guest.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.c | 19 ++-
target/i386/cpu.h | 1 +
target/i386/kvm.c | 23 +++
3 files changed, 42 insertions(+), 1 deletion(-)
diff
From: Chao Peng
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Chao Peng
Signed-off-by: Luwei Kang
---
target/i386/cpu.h | 22 ++
target/i386/kvm.c | 51
Add more AVX512 feature bits, include AVX512DQ, AVX512IFMA,
AVX512BW, AVX512VL, AVX512VBMI. Its spec can be found at:
https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
Signed-off-by: Luwei Kang
---
target-i386/cpu.c | 14 +-
target-i386/cpu.h | 5 +
2
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