On 13/04/2023 16:01, Shivaprasad G Bhat wrote:
Add test for vextractbm, vextractwm, vextractdm and vextractqm
instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
Based on the test case written by John Platts posted at [1]
References:
[1]: https://gitlab.com/qemu-project/qemu/-/iss
On 13/04/2023 16:01, Shivaprasad G Bhat wrote:
In function do_extractm() the mask is calculated as
dup_const(1 << (element_width - 1)). '1' being signed int
works fine for MO_8,16,32. For MO_64, on PPC64 host
this ends up becoming 0 on compilation. The vextractdm
uses MO_64, and it ends up hav
On 10/10/2022 16:42, Richard Henderson wrote:
On 10/10/22 12:13, Lucas Mateus Castro(alqotel) wrote:
+/* test if +Inf or -Inf */
+static void gen_is_any_inf(unsigned vece, TCGv_vec t, TCGv_vec b)
+{
+ uint64_t exp_msk = (vece == MO_32) ? (uint32_t)EXP_MASK_SP :
EXP_MASK_DP;
+ uint64_t
On 22/09/2022 13:32, Alex Bennée wrote:
"Lucas Mateus Castro(alqotel)" writes:
This patch series aim to make easier to set up a compilation and CI
environment on PPC64 and PPC64LE machines.
Queued to testing/next, thanks.
Do we have a donated ppc64 machine to add to the custom runners?
I
On 15/09/2022 12:54, Thomas Huth wrote:
On 14/09/2022 13.41, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
ninja-build is missing from the RHEL environment, so a system prepared
with that script would still fail to compile QEMU.
Tested on a Fedora 36
Signed-off-
On 06/09/2022 16:52, Daniel Henrique Barboza wrote:
Lucas,
If you're still interested, patches 1-4 are worth re-sending in separate.
You'll need to address Daniel's comments on patch 1. The other 3 patches
LGTM.
Patches 5-8 can wait. We're not certain about Unicamp's Minicloud
availability in
On 18/08/2022 12:32, Richard Henderson wrote:
On 8/17/22 09:57, Lucas Mateus Castro(alqotel) wrote:
+void sigfpe_handler(int sig, siginfo_t *si, void *ucontext)
+{
+ uint64_t t;
+ uint64_t ch = 0x5fcfffe4965a17e0ull;
+ asm (
+ "stfd 2, %0\n\t"
+ : "=m"(t)
+ :
+
ping
Any interest in this?
On 12/07/2022 11:51, Lucas Mateus Martins Araujo e Castro wrote:
Hi everyone!
I would like gauge the interest in using Minicloud's infrastructure[1]
for the CI, talking with some people from there they are interested.
It has both ppc64 and pp64le images, mul
It's missing from the title but this is a v2.
v1 id:
Message-Id: <20220803122217.20847-1-lucas.ara...@eldorado.org.br>
On 05/08/2022 11:15, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Changes in v2:
- Completely reworked the solution:
* Created re_bi
On 05/08/2022 13:20, Alex Bennée wrote:
"Lucas Mateus Castro(alqotel)" writes:
From: "Lucas Mateus Castro (alqotel)"
Changes in v2:
- Completely reworked the solution:
* Created re_bias in FloatFmt, it is 3/4 of the total exponent
range of a FP type
I thought this m
On 12/07/2022 06:35, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Break a cyclic dependency between int128 and host-utils.
Reviewed-by: Lucas Mateus Castro
Signed-off-by: Marc-André Lureau
---
include/qemu/host-utils.h | 3 -
include/qemu/int128.h | 3 +
util/host-
On 03/08/2022 15:16, Richard Henderson wrote:
On 8/3/22 10:45, Lucas Mateus Martins Araujo e Castro wrote:
On 03/08/2022 13:18, Richard Henderson wrote:
On 8/3/22 05:22, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
As mentioned in the
On 03/08/2022 13:18, Richard Henderson wrote:
On 8/3/22 05:22, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
As mentioned in the functions float_overflow_excp and
float_underflow_excp, the result should be adjusted as mentioned in the
ISA (subtracted 192/1536 from
On 29/07/2022 17:44, Daniel Henrique Barboza wrote:
On 7/29/22 14:21, Richard Henderson wrote:
This is, technically, a regression from 6.2, so it's not
implausible to apply before rc1. Thoughts?
In gitlab #1097 the author comments that:
https://gitlab.com/qemu-project/qemu/-/issues/1097#n
On 27/07/2022 14:09, Daniel P. Berrangé wrote:
On Wed, Jul 27, 2022 at 01:36:25PM -0300, Lucas Mateus Castro(alqotel) wrote:
Currently the run script uses 'readlink -e' but the image only has the
busybox readlink, this commit add the coreutils package which
contains the readlink with the '-e'
On 15/07/2022 17:54, Víctor Colombo wrote:
Implementation for instructions hashst and hashchk, which were added
in Power ISA 3.1B.
It was decided to implement the hash algorithm from ground up in this
patch exactly as described in Power ISA.
Signed-off-by: Víctor Colombo
---
target/ppc/excp_
Reviewed-by: Lucas Mateus Castro
On 15/07/2022 17:54, Víctor Colombo wrote:
Implementation for instructions hashstp and hashchkp, the privileged
versions of hashst and hashchk, which were added in Power ISA 3.1B.
Signed-off-by: Víctor Colombo
---
target/ppc/excp_helper.c |
On 15/07/2022 17:54, Víctor Colombo wrote:
Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were
introduced by the Power ISA 3.1B. They are used by the new instructions
hashchk(p) and hashst(p).
The ISA states that the Operating System should generate the value for
these registers
Hi everyone!
I would like gauge the interest in using Minicloud's infrastructure[1]
for the CI, talking with some people from there they are interested. It
has both ppc64 and pp64le images, multiple versions of 4 distros
(Ubuntu, Fedora, Debian and CentOS).
I've made a initial test setup in
Hi everyone!
I would like gauge the interest in using Minicloud's infrastructure[1]
for the CI, talking with some people from there they are interested. It
has both ppc64 and pp64le images, multiple versions of 4 distros
(Ubuntu, Fedora, Debian and CentOS).
I've made a initial test setup in
On 09/06/2022 10:56, Peter Maydell wrote:
On Mon, 6 Jun 2022 at 15:34, Lucas Mateus Castro(alqotel)
wrote:
---
Currently there's a disagreement between the checkpatch code and the
documentation, this RFC just changes the checkpatch to match the
documentation.
But there was a discussion in 20
On 02/06/2022 16:10, Daniel Henrique Barboza wrote:
Commit c29018cc7395 added an env->fpscr OR operation using a ternary
that checks if 'error' is not zero:
env->fpscr |= error ? FP_FEX : 0;
However, in the current body of do_fpscr_check_status(), 'error' is
granted to be always non-zero
On 02/06/2022 11:14, Daniel Henrique Barboza wrote:
Coverity is not thrilled about the multiply operations being done in
ger_rank8() and ger_rank2(), giving an error like the following:
Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "sextract32(a, 4 * i
On 20/05/2022 12:47, Richard Henderson wrote:
On 5/20/22 06:51, Lucas Mateus Castro(alqotel) wrote:
+ if (acc) {
+ aux_acc = at[i].VsrSF(j);
+ if (!neg_mul && !neg_acc) {
+ r = float32_add(r, aux_acc, excp_ptr);
+
ping
On 20/04/2022 16:40, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
This patch series is an implementation of the vector divide, vector
divide extended and vector modulo instructions from PowerISA 3.1
The first patch are Matheus' patch, used here since the divs2
On 08/05/2022 00:48, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
+{
+ arg_MMIRR_XX3 m;
+ m.xa = a->xa;
+ m.xb = a->xb;
+ m.xt = a->xt;
+ m.pmsk = 0xFF;
+ m.ymsk = 0xF;
+ m.xmsk = 0xF;
+ return do_ger_MMIRR_XX3(ctx, &m, helper);
}
Is
On 27/04/2022 17:51, Daniel Henrique Barboza wrote:
On 4/27/22 03:42, Joel Stanley wrote:
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley
---
MMA support for TCG is on the list so I think it makes sense for this to
land after those are merged.
I believe you mean this
On 08/05/2022 00:41, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 10c6d7ae43..348a898950 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -238,6 +238,7 @@ typedef union _ppc_vsr_t {
typedef ppc_vsr
On 08/05/2022 01:27, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
There's a discrepancy between this implementation and mambo/the
hardware where implementing it with float64_mul then float64r32_muladd
sometimes results in an incorrect result after an underflow,
On 08/05/2022 01:24, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
+static inline float32 float32_neg(float32 a)
+{
+ if (((a & 0x7f80) == 0x7f80) && (a & 0x007f)) {
+ return a;
+ } else {
+ return float32_chs(a);
+ }
+}
This
On 08/05/2022 01:03, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floatin
Something I forgot to mention in the cover letter, the XVFGER
instructions accumulate the exception status and at the end set the
FPSCR and take a Program interrupt on a trap-enabled exception, but as
the exception functions are currently set up in target/ppc/fpu_helper.c
a call to set a FPSCR
On 26/04/2022 21:26, Richard Henderson wrote:
On 4/26/22 05:50, Lucas Mateus Castro(alqotel) wrote:
+#define VSXGER16(NAME, ORIG_T,
OR_EL) \
+ void NAME(CPUPPCState *env, uint32_t a_r, uint32_t
b_r, \
+ uint32_t at_r, uint32_t mask
On 26/04/2022 20:40, Richard Henderson wrote:
On 4/26/22 05:50, Lucas Mateus Castro(alqotel) wrote:
+%xx_at 23:3 !function=times_4
+@XX3_at .. ... .. . . ... &XX3
xt=%xx_at xb=%xx_xb
Hmm. Depends, I suppose on whether you want acc[0-7] or vsr[0-28]
I m
On 20/04/2022 22:17, Bin Meng wrote:
From: Bin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events a
On 11/04/2022 22:51, Richard Henderson wrote:
On 4/5/22 12:55, Lucas Mateus Castro(alqotel) wrote:
+
+#define DO_VDIV_VMOD(NAME, SZ, DIV,
SIGNED) \
+static void NAME(TCGv_i##SZ t, TCGv_i##SZ a, TCGv_i##SZ
b) \
+{ \
+ /* \
+ * If N/0 the instruc
On 30/03/2022 18:06, Richard Henderson wrote:
On 3/30/22 14:25, Lucas Mateus Castro(alqotel) wrote:
+#define TRANS_VDIV_VMOD(FLAGS, NAME, VECE, FNI4_FUNC,
FNI8_FUNC) \
+static bool trans_##NAME(DisasContext *ctx, arg_VX
*a) \
+{ \
+ static const GVecGen3 op[2] =
{
On 04/03/2022 11:07, Cédric Le Goater wrote:
On 3/4/22 12:08, Lucas Mateus Martins Araujo e Castro wrote:
On 02/03/2022 20:55, Fabiano Rosas wrote:
Howard Spoelstra writes:
On Wed, Mar 2, 2022 at 9:11 PM BALATON Zoltan
wrote:
On Wed, 2 Mar 2022, Howard Spoelstra wrote:
Hi all,
I
On 02/03/2022 20:55, Fabiano Rosas wrote:
Howard Spoelstra writes:
On Wed, Mar 2, 2022 at 9:11 PM BALATON Zoltan wrote:
On Wed, 2 Mar 2022, Howard Spoelstra wrote:
Hi all,
I noticed qemu-system-ppc running OSX guests does not get to the desktop
or
does not display the menu bars.
Cc-in
On 19/11/2021 06:18, Richard Henderson wrote:
On 11/18/21 2:25 PM, Lucas Mateus Castro (alqotel) wrote:
+ if ((fpscr & FP_VXSOFT) && (fpscr_ve != 0)) {
+ error = POWERPC_EXCP_FP_VXSOFT;
+ } else if ((fpscr & FP_OX) && (fpscr & FP_OE)) {
+ error = POWERPC_EXCP_FP_OX;
+ } e
On 09/11/2021 13:44, Daniel Henrique Barboza wrote:
On 10/20/21 09:57, Lucas Mateus Castro (alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directl
On 10/11/2021 05:19, Mark Cave-Ayland wrote:
On 20/10/2021 13:57, Lucas Mateus Castro (alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status
On 10/11/2021 03:56, Cédric Le Goater wrote:
On 11/9/21 17:37, Daniel Henrique Barboza wrote:
On 10/20/21 09:57, Lucas Mateus Castro (alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR
On 14/07/2021 08:23, Lucas Mateus Martins Araujo e Castro wrote:
On 08/07/2021 15:09, Richard Henderson wrote:
On 7/8/21 9:49 AM, Lucas Mateus Castro (alqotel) wrote:
+++ b/target/ppc/cpu.h
@@ -1327,6 +1327,26 @@ void store_40x_dbcr0(CPUPPCState *env,
uint32_t val);
void store_40x_sler
On 08/07/2021 15:09, Richard Henderson wrote:
On 7/8/21 9:49 AM, Lucas Mateus Castro (alqotel) wrote:
+++ b/target/ppc/cpu.h
@@ -1327,6 +1327,26 @@ void store_40x_dbcr0(CPUPPCState *env,
uint32_t val);
void store_40x_sler(CPUPPCState *env, uint32_t val);
void store_booke_tcr(CPUPPCState
On 15/06/2021 02:42, David Gibson wrote:
On Thu, Jun 10, 2021 at 01:46:47PM -0300, Lucas Mateus Castro (alqotel) wrote:
Moved functions in mmu_helper.c that should be compiled in build to
"should be compiled in build" is not very clear to me. What's the
distinction between both the files.
Loo
On 15/06/2021 02:38, David Gibson wrote:
On Thu, Jun 10, 2021 at 01:46:46PM -0300, Lucas Mateus Castro (alqotel) wrote:
The function ppc_tlb_invalid_all is now a no op when compiling without TCG.
Signed-off-by: Lucas Mateus Castro (alqotel)
Hm, I think I suggested making ppc_tlb_invalidate_
Hi everyone,
I'm working on cleaning up some of the changes to enable the disable-tcg
option on PPC, right now focusing on target/ppc/excp_helper.c and
target/ppc/mmu_helper.c as these files have functions that are needed in
a !TCG build but also contains code that doesn't compile in a !TCG
b
On 27/05/2021 14:56, Bruno Larsen (billionai) wrote:
Documented the removal of the HMP command info cpustats
Signed-off-by: Bruno Larsen (billionai)
---
docs/system/removed-features.rst | 5 +
1 file changed, 5 insertions(+)
Reviewed-by: Lucas Mateus
--
Lucas Mateus M. Araujo e Castro
On 17/05/2021 00:58, David Gibson wrote:
On Thu, May 13, 2021 at 06:44:01PM -0500, Richard Henderson wrote:
65;6401;1c> On 5/13/21 9:03 AM, Lucas Mateus Martins Araujo e Castro wrote:
tlb_set_page is called by many ppc_hash64_handle_mmu_fault,
ppc_radix64_handle_mmu_fault
On 12/05/2021 15:34, Richard Henderson wrote:
On 5/12/21 9:08 AM, Bruno Larsen (billionai) wrote:
From: "Lucas Mateus Castro (alqotel)"
Added tlb_set_page and tlb_set_page_with_attrs to the
stubbed functions in exec-all.h as it is needed
in some functions when compiling without TCG
Signed-o
On 03/05/2021 01:24, David Gibson wrote:
On Fri, Apr 30, 2021 at 03:40:46PM -0300, Lucas Mateus Castro (alqotel) wrote:
The functions ppc_store_lpcr, ppc_hash64_filter_pagesizes and
ppc_hash64_unmap_hptes have been moved to mmu-misc.h since they are
not needed in a !TCG context and mmu-hash64
On 03/05/2021 01:34, David Gibson wrote:
On Fri, Apr 30, 2021 at 03:40:47PM -0300, Lucas Mateus Castro (alqotel) wrote:
Moved h_enter, remove_hpte, h_remove, h_bulk_remove,h_protect and
h_read to spapr_hcall_tcg.c, added h_tcg_only to be used in a !TCG
environment in spapr_hcall.c and changed b
Thanks, it will be quite helpful.
Also, I agree with Bruno including this information somewhere would be quite
good in my opinion.
From: Fabiano Rosas
Sent: Monday, May 3, 2021 7:21 PM
To: Lucas Mateus Martins Araujo e Castro ;
qemu-devel@nongnu.org ; qemu
>> spapr_hcall.c:
>> function h_enter call ppc_hash64_hpte_page_shift_noslb,
>> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
>> function remove_hpte call ppc_hash64_map_hptes, ppc_hash64_unmap_hptes
>> and ppc_hash64_tlb_flush_hpte
>> function h
>> spapr_hcall.c:
>> function h_enter call ppc_hash64_hpte_page_shift_noslb,
>> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
>> function remove_hpte call ppc_hash64_map_hptes, ppc_hash64_unmap_hptes
>> and ppc_hash64_tlb_flush_hpte
>> function h_protect call ppc_hash64_map_hptes,
Hi, I have been working on billionai's patch to enable the --disable-tcg option
on PowerPC and one of the problems is that 5 files in hw/ppc use functions
implemented in mmu-hash64.c which is not compiled with --disable-tcg, I'd like
to know how to correct the spapr function call, should I
*
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