2013/3/31 Peter Crosthwaite :
> Hi Kuo-Jung
>
> I think you may have accidentally dropped your subject line and
> promoted your long commit message to subject line. Looks better in
> previous versions.
>
Yes, it's an accident, I'll fix it later.
> On Mon, Mar 25
2013/3/29 Peter Crosthwaite :
> Hi Kuo-Jung,
>
> On Mon, Mar 25, 2013 at 10:09 PM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> The Faraday FTDMAC020 provides eight configurable
>> channels for the memory-to-memory, memory-to-peripheral,
>> peripheral-
2013/3/29 Peter Crosthwaite :
> Hi Kuo-Jung,
>
> On Mon, Mar 25, 2013 at 10:10 PM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> The FTSPI020 is an integrated SPI Flash controller
>> which supports up to 4 flash chips.
>>
>> Signed-off-by: Kuo-Ju
2013/3/28 Peter Crosthwaite :
> Hi Kuo Jung,
>
> On Thu, Mar 28, 2013 at 1:24 PM, Kuo-Jung Su wrote:
>> 2013/3/28 Peter Crosthwaite :
>>> Hi Kuo-Jung,
>>>
>>> On Mon, Mar 25, 2013 at 10:09 PM, Kuo-Jung Su wrote:
>>>> From: Kuo-Jung Su
>
2013/3/28 Peter Crosthwaite :
> Hi Kuo-Jung,
>
> On Mon, Mar 25, 2013 at 10:09 PM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> The FTDDRII030 is a DDRII SDRAM controller which is responsible for
>> SDRAM initialization.
>>
>> Signed-off-by:
From: Kuo-Jung Su
The FTI2C010 is a simple I2C master controller.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |6 ++
hw/fti2c010.c | 224 +++
hw/fti2c010.h | 74
From: Kuo-Jung Su
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|3 +-
hw/arm/ftplat_a369.c| 31 +++
hw/arm/ftplat_a369soc.c | 17 ++
hw/faraday.h|3 +
hw/ftssp010.c | 504
From: Kuo-Jung Su
Wolfson WM8731 is a simple audio codec for embedded systems.
It has 2 input and 1 output ports:
** Input **
1. Linue-In
2. Microphone
** Output **
1. Headphone out
BTW it's based on hw/wm8750.c with 16-bit I2S support by default.
Signed-off-by: Kuo-Ju
From: Kuo-Jung Su
The FTRTC011 QEMU model is implemented without calender functions.
It acts in counter mode only, all the time & timezone conversion
relies on the c runtime library. (i.e. mktime(), localtime() ...etc)
Signed-off-by: Kuo-Jung Su
---
tests/Makefile|3 +
t
From: Kuo-Jung Su
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC.
However the optional
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
---
hw/Makefile.objs |1 +
hw/arm/spitz.c |9 +++--
hw/arm/z2.c|9 +++--
hw/audio.c | 81 +++
hw/audio.h | 56
From: Kuo-Jung Su
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block is the only channel
From: Kuo-Jung Su
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm
From: Kuo-Jung Su
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16 handshaking channels in the
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
---
include/qemu/bitops.h | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..64cbb04 100644
--- a/include/qemu/bitops.h
From: Kuo-Jung Su
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports half-word data transfer
From: Kuo-Jung Su
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|2 +
hw/arm/ftplat_a369.c| 96
From: Kuo-Jung Su
The FTSDC010 is a simple MMC/SD host controller and
many of its registers are similar to Arm PrimeCell PL181.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |7 +
hw/ftsdc010.c | 359
From: Kuo-Jung Su
The FTSPI020 is an integrated SPI Flash controller
which supports up to 4 flash chips.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |2 +-
hw/arm/ftplat_a369.c | 16 +++
hw/ftspi020.c| 341 ++
hw/ftspi020
From: Kuo-Jung Su
The FTTMR010 provides three independent sets of sub-timers.
Two match registers are provided for each sub-timer, whenever
the value of the match registers equals any one value of the
sub-timers, the timer interrupt will be immediately triggered.
And it would also issue an
From: Kuo-Jung Su
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |8 ++
hw/ftddrii030.c | 192 +++
3
From: Kuo-Jung Su
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer at both
Linux and WINCE.
It
From: Kuo-Jung Su
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or
From: Kuo-Jung Su
It's used to manage AHB slave devices
and also the AHB remap function for slave4 & slave6.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c |9 ++
hw/ftahbc020.c | 216 +
From: Kuo-Jung Su
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs|2 +-
hw/arm/ftplat_a369soc.c | 10 ++
hw/ftpwmtmr010.c| 261 +++
hw/ftpwmtmr010.h
From: Kuo-Jung Su
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
From: Kuo-Jung Su
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode provides a periodic
From: Kuo-Jung Su
These patches introduce Faraday A369 SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
The partial version of faraday cpu datasheet with only
the CP15 and MPU description are available at my
From: Kuo-Jung Su
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge-rising/falling triggered
From: Kuo-Jung Su
This patch includes the single core support to FA606TE, FA626TE,
FA616TE and FA726TE with CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su
---
target-arm/cpu.c | 52 +++
target-arm/cpu.h |6 +++-
target
2013/3/18 Peter Maydell :
> On 18 March 2013 09:56, Kuo-Jung Su wrote:
>> The FTDDRII030 is responsible for SDRAM initialization.
>> Which means the DDRII SDRAM would not be stabilized until the
>> SDRAM is correctly initialized.
>> =>
>> In QEMU, the memo
2013/3/18 Peter Crosthwaite :
> On Mon, Mar 18, 2013 at 11:12 AM, Kuo-Jung Su wrote:
>> 2013/3/16 Peter Crosthwaite :
>>> Hi Kuo-Jung,
>>>
>>> On Fri, Mar 15, 2013 at 11:13 PM, Kuo-Jung Su wrote:
>>>> From: Kuo-Jung Su
>>>>
>>
2013/3/16 Peter Crosthwaite :
> On Fri, Mar 15, 2013 at 11:15 PM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> The FTI2C010 is a simple I2C master controller.
>>
>> Signed-off-by: Kuo-Jung Su
>> ---
>> hw/arm/Makefile.objs |1 +
>&
2013/3/16 Peter Crosthwaite :
> Hi Kuo-Jung,
>
> On Fri, Mar 15, 2013 at 11:13 PM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> The FTDDRII030 is a DDRII SDRAM controller which is responsible for
>> SDRAM initialization.
>> In QEMU we emulate only the SDR
2013/3/15 Peter Maydell :
> On 15 March 2013 13:15, Kuo-Jung Su wrote:
>> default-configs/arm-softmmu.mak |1 +
>> hw/Makefile.objs|2 +
>> hw/arm/Makefile.objs| 21 ++
>> hw/arm/faraday.h| 61
>> hw/ar
From: Kuo-Jung Su
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we emulate only the SDRAM enable function.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |9 +++
hw/arm/ftddrii030.c
From: Kuo-Jung Su
This patch includes the single core support to FA606TE, FA626TE,
FA616TE and FA726TE with CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su
---
target-arm/cpu.c | 52 +++
target-arm/cpu.h |6 +++-
target
From: Kuo-Jung Su
The FTSPI020 is an integrated SPI Flash controller
which supports up to 4 flash chips.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369.c | 16 +++
hw/arm/ftspi020.c | 337 +
hw/arm
From: Kuo-Jung Su
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |3 +
hw/arm/faraday.h | 52 ++
hw
From: Kuo-Jung Su
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer at both
Linux and WINCE.
It
From: Kuo-Jung Su
The FTSDC010 is a simple MMC/SD host controller and
many of its registers are similar to Arm PrimeCell PL181.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |7 +
hw/arm/ftsdc010.c | 354
From: Kuo-Jung Su
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode provides a periodic
From: Kuo-Jung Su
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
---
include/qemu/bitops.h | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..64cbb04 100644
--- a/include/qemu/bitops.h
From: Kuo-Jung Su
The FTSSP010 is a multi-function synchronous serial port interface
controller which supports SSP, SPI, I2S, AC97 and SPDIF.
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday.h
From: Kuo-Jung Su
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC.
However the optional
From: Kuo-Jung Su
The FTI2C010 is a simple I2C master controller.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |6 ++
hw/arm/fti2c010.c | 212 +
hw/arm/fti2c010.h | 71
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
---
hw/Makefile.objs |1 +
hw/arm/spitz.c |9 +++--
hw/arm/z2.c|9 +++--
hw/audio_codec.c | 81 +++
hw/audio_codec.h | 56
From: Kuo-Jung Su
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block is the only channel
From: Kuo-Jung Su
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16 handshaking channels in the
From: Kuo-Jung Su
The FTTMR010 provides three independent sets of sub-timers.
Two match registers are provided for each sub-timer, whenever
the value of the match registers equals any one value of the
sub-timers, the timer interrupt will be immediately triggered.
And it would also issue an
From: Kuo-Jung Su
The FTRTC011 QEMU model is implemented without calender functions.
It acts in counter mode only, all the time & timezone conversion
relies on the c runtime library. (i.e. mktime(), localtime() ...etc)
Signed-off-by: Kuo-Jung Su
---
tests/Makefile|3 +
t
From: Kuo-Jung Su
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports half-word data transfer
From: Kuo-Jung Su
Wolfson WM8731 is a simple audio codec for embedded systems.
It has 2 input and 1 output ports:
** Input **
1. Linue-In
2. Microphone
** Output **
1. Headphone out
BTW it's based on hw/wm8750.c with 16-bit I2S support by default.
Signed-off-by: Kuo-Ju
From: Kuo-Jung Su
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 ++
hw/arm/ftpwmtmr010.c | 258 +
hw/arm
From: Kuo-Jung Su
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm
From: Kuo-Jung Su
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge-rising/falling triggered
From: Kuo-Jung Su
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
From: Kuo-Jung Su
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we emulate only the SDRAM enable function.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |9 +++
hw/arm/ftddrii030.c
From: Kuo-Jung Su
It's used to perform AHB remap and QEMU RAM initialization
when the SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 +++
hw/arm/ftahbc020.c|
From: Kuo-Jung Su
These patches introduce Faraday A369 SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
The partial version of faraday cpu datasheet with only
the CP15 and MPU description are available at my
From: Kuo-Jung Su
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |3 +
hw/arm/faraday.h | 52 ++
hw
From: Kuo-Jung Su
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
From: Kuo-Jung Su
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 ++
hw/arm/ftpwmtmr010.c | 258 +
hw/arm
From: Kuo-Jung Su
This patch includes the single core support to FA606TE, FA626TE,
FA616TE and FA726TE with CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su
---
target-arm/cpu.c | 52 +++
target-arm/cpu.h |6 +++-
target
From: Kuo-Jung Su
It's used to perform AHB remap and QEMU RAM initialization
when the SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 +++
hw/arm/ftahbc020.c|
From: Kuo-Jung Su
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm
From: Kuo-Jung Su
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge-rising/falling triggered
From: Kuo-Jung Su
These patches introduce Faraday A369 SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
The partial version of faraday cpu datasheet with only
the CP15 and MPU description are available at my
From: Kuo-Jung Su
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC.
However the optional
From: Kuo-Jung Su
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode provides a periodic
From: Kuo-Jung Su
The FTTMR010 provides three independent sets of sub-timers.
Two match registers are provided for each sub-timer, whenever
the value of the match registers equals any one value of the
sub-timers, the timer interrupt will be immediately triggered.
And it would also issue an
From: Kuo-Jung Su
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or
From: Kuo-Jung Su
The FTSDC010 is a simple MMC/SD host controller and
many of its registers are similar to Arm PrimeCell PL181.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |7 +
hw/arm/ftsdc010.c | 358
From: Kuo-Jung Su
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer at both
Linux and WINCE.
It
From: Kuo-Jung Su
The FTSSP010 is a multi-function synchronous serial port interface
controller which supports SSP, SPI, I2S, AC97 and SPDIF.
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday.h
From: Kuo-Jung Su
The FTSPI020 is an integrated SPI Flash controller
which supports up to 4 flash chips.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369.c | 16 +++
hw/arm/ftspi020.c | 340 +
hw/arm
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
---
include/qemu/bitops.h | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..64cbb04 100644
--- a/include/qemu/bitops.h
From: Kuo-Jung Su
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm
From: Kuo-Jung Su
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports half-word data transfer
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
---
hw/Makefile.objs |1 +
hw/arm/spitz.c |9 +++--
hw/arm/z2.c|9 +++--
hw/audio_codec.c | 81 +++
hw/audio_codec.h | 56
From: Kuo-Jung Su
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
From: Kuo-Jung Su
Wolfson WM8731 is a simple audio codec for embedded systems.
It has 2 input and 1 output ports:
** Input **
1. Linue-In
2. Microphone
** Output **
1. Headphone out
BTW it's based on hw/wm8750.c with 16-bit I2S support by default.
Signed-off-by: Kuo-Ju
From: Kuo-Jung Su
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 ++
hw/arm/ftpwmtmr010.c | 264 +
hw/arm
From: Kuo-Jung Su
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16 handshaking channels in the
From: Kuo-Jung Su
It's used to perform AHB remap and QEMU RAM initialization
when the SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 +++
hw/arm/ftahbc020.c|
From: Kuo-Jung Su
The FTI2C010 is a simple I2C master controller.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |6 ++
hw/arm/fti2c010.c | 216 +
hw/arm/fti2c010.h | 71
From: Kuo-Jung Su
The FTRTC011 QEMU model is implemented without calender functions.
It acts in counter mode only, all the time & timezone conversion
relies on the c runtime library. (i.e. mktime(), localtime() ...etc)
Signed-off-by: Kuo-Jung Su
---
tests/Makefile|3 +
t
From: Kuo-Jung Su
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we emulate only the SDRAM enable function.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |9 +++
hw/arm/ftddrii030.c
From: Kuo-Jung Su
This patch includes the single core support to FA606TE, FA626TE,
FA616TE and FA726TE with CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su
---
target-arm/cpu.c | 52 +++
target-arm/cpu.h |6 +++-
target
From: Kuo-Jung Su
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block is the only channel
From: Kuo-Jung Su
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |3 +
hw/arm/faraday.h | 59
hw
From: Kuo-Jung Su
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge-rising/falling triggered
From: Kuo-Jung Su
These patches introduce Faraday A369 SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
The partial version of faraday cpu datasheet with only
the CP15 and MPU description are available at my
2013/3/7 Paolo Bonzini :
>
>> From Makefile.target, qtest is built when you build softmmu target.
>> I guess there is no need to add "--enable-qtest" option. However, I
>> don't know how to run qtest...
>
> make check-qtest-arm
>
> Paolo
Got it, thanks.
--
Best wishes,
Kuo-Jung Su
2013/3/6 Paolo Bonzini :
> Il 06/03/2013 08:27, Kuo-Jung Su ha scritto:
>> It provides separate second, minute, hour, and day counters. The second
>> counter is toggled each second, the minute counter is toggled each minute,
>> the hour counter is toggled each hour, and the d
2013/3/7 Kuo-Jung Su :
> 2013/3/6 Paolo Bonzini :
>>> > > It doesn't work while running under ROM mode. ( no -kernel )
>>> > > Because Faraday SoC Platform usually designed to boot from ROM and
>>> > > followed by an AHB remapping process (i.e.
>
> case NAND_CMD_BLOCKERASE2:
> + s->addr &= 0xff;
>
> Regards,
> Peter
>
I've verified that it works to me, too. So it's should be a
replacement of my buggy one.
> That's why I didn't give it a
>> reviewed-by tag. If you can provide a reasonably coherent explanation
>> of why it doesn't break anything else with reference to a decent
>> datasheet, you could convince me it's OK.
>>
>> -- PMM
>>
--
Best wishes,
Kuo-Jung Su
2013/3/7 Peter Crosthwaite :
> Hi Kuo Jung, Peter,
>
> This patch fixes bugs for us in Zynq Nand (cc Wendy Liang). Can we get
> a cherry pick of this?
>
Why not? Please go ahead.
> Regards,
> Peter
>
> On Wed, Mar 6, 2013 at 5:27 PM, Kuo-Jung Su wrote:
>&g
uffers this bug because of the BBT, which stands for
Bad Block Table.
In other words, the u-boot / linux usually starts with a bunch of bad block scan
on block boundary (i.e. 64KB, 128KB).
While the addr is a uint32_t, right-shift 24 bits would always clear
address long enough for the incoming new address, but things would go
mad, if it's a uint64_t.
--
Best wishes,
Kuo-Jung Su
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