3 09:10
To: peter.mayd...@linaro.org
Cc: Kinsey Moore ; qemu-devel@nongnu.org;
phi...@linaro.org
Subject: Re: [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs
+PMM (I think this one might have fallen throught the cracks)
Best regards,
Francisco Iglesias
On [2023 Jun 18] Sun 00:50:47, Philippe Mat
for platforms where it is available. This patch
has been tested using the lwIP stack with a Xilinx-supplied driver from
their embeddedsw repository.
Signed-off-by: Kinsey Moore
---
hw/arm/xlnx-versal.c | 12 +++-
hw/arm/xlnx-zynqmp.c | 11 ++-
include/hw/arm/xlnx
Thanks for the review. I'll get this updated and sent back out as soon as I've
tested it.
Kinsey
-Original Message-
From: Francisco Iglesias
Sent: Friday, June 16, 2023 3:28 AM
To: Kinsey Moore
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH] hw/arm/xlnx: Connect secondary
In testing RTEMS on the ZynqMP platform, I noticed that priority queues
were not functioning properly. I tracked this down to an unconnected
interrupt source in the Cadence GEM when multiple priority queues are
configured. I'm not sure if the Cadence IP can actually be configured
for separate inter
for platforms where it is available. This patch
has been tested using the lwIP stack with a Xilinx-supplied driver from
their embeddedsw repository.
Signed-off-by: Kinsey Moore
---
hw/arm/xlnx-versal.c | 1 +
hw/arm/xlnx-zynqmp.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/hw/arm/xlnx
