[PATCH 1/4] target/rx: Set exception vector base to 0xffffff80

The documentation says the vector is at 0xff80, instead of the previous value of 0xffc0. That value must have been a bug because the standard vector values (20, 21, 23, 25, 30) were all past the end of the array. Signed-off-by: Keith Packard --- target/rx/helper.c | 2 +- 1 file changed

[PATCH 4/4] rx: Support loading of ELF files too

The existing loader supports raw binary blobs with the entry point defined as the start of the blob. Add support for loading ELF files by first checking if the provided filename has a valid ELF header, falling back to the existing loader code when that fails. Signed-off-by: Keith Packard --- hw

[PATCH 0/4] Renesas RX target fixes (v2)

d for this model to be usable; without this, it's fairly easy to use the loader device; that just requires the loaded image to include the exception vectors with the correct reset vector value. Keith Packard (4): target/rx: Set exception vector base to 0xff80 target/rx: Remove TCG_

[PATCH 2/4] target/rx: Remove TCG_CALL_NO_WG from helpers which write env

. This seems to also mean that functions which set condition codes may also not use this flag Signed-off-by: Keith Packard --- target/rx/helper.h | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/rx/helper.h b/target/rx/helper.h index

[PATCH 3/4] hw/rx: Reset the CPU at qemu reset time

This ensure that the CPU gets reset every time QEMU resets. Use either the kernel entry point or the reset vector if no kernel was loaded. Signed-off-by: Keith Packard --- hw/rx/rx-gdbsim.c | 36 +++- target/rx/cpu.c | 9 ++--- target/rx/cpu.h | 3

Re: [PATCH 4/5] target/rx: Load reset vector from memory after first run

> > By delaying the load of the reset vector to the reset_exit phase, > > you can always load from rom. > I'm not sure how -- the ROM image is discarded when it gets loaded into > read-only memory. If loaded to read-write memory, I bet it would > stay around. Ah, but by delaying until after cpu_

Re: [PATCH 4/5] target/rx: Load reset vector from memory after first run

> So I'm OK with this patch doing this the way it does, > except that I have one question: what's that > process_queued_cpu_work() call doing? We don't need > that on the Arm equivalent... Yup, I needed that because I was running this bit at cpu_reset_hold time, not waiting until after cpu reset

Re: [PATCH 4/5] target/rx: Load reset vector from memory after first run

From: Richard Henderson Date: Sat, 15 Feb 2025 10:24:05 -0800 > By delaying the load of the reset vector to the reset_exit phase, > you can always load from rom. I'm not sure how -- the ROM image is discarded when it gets loaded into read-only memory. If loaded to read-write memory, I bet it wou

Re: [PATCH 3/5] target/rx: Reset the CPU at qemu reset time

From: Peter Maydell Date: Mon, 17 Feb 2025 09:53:58 + > Reset of devices not plugged into buses (of which CPUs > are the most common kind) is a mess. But having them > call qemu_register_reset() themselves in their own > realize method isn't the usual workaround. Instead we > get the board co

Re: [PATCH 5/5] target/rx: Remove TCG_CALL_NO_WG from helpers which write env

> Functions which modify virtual machine state (such as virtual > registers stored in memory) must not be marked TCG_CALL_NO_WG as that > tells the optimizer that virtual registers values already loaded in > machine registers are still valid, hence discards any changes which > these helpers may ha

[PATCH 2/5] target/rx: Set exception vector base to 0xffffff80

The documentation says the vector is at 0xff80, instead of the previous value of 0xffc0. That value must have been a bug because the standard vector values (20, 21, 23, 25, 30) were all past the end of the array. Signed-off-by: Keith Packard --- target/rx/helper.c | 2 +- 1 file changed

[PATCH 4/5] target/rx: Load reset vector from memory after first run

The ROM images all get deleted as they've been loaded to memory, so we can't go fetch the reset vector from there. Instead, fetch it from memory. To make that work, we need to execute the delayed mmu setup function tcg_commit_cpu as that wires up memory dispatching. Signed-off-by: Kei

[PATCH 1/5] hw/rx: Allow execution without either bios or kernel

Users can use -device loader to get an ELF file loaded to memory, so we don't need to require one of these options. Signed-off-by: Keith Packard --- hw/rx/rx-gdbsim.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 88c8f12c10..4afd77efd5 1

[PATCH 0/5] Renesas RX target fixes

ector found in the exception table and then re-loading that vector during subsequent reset operations. With these fixes, the picolibc CI tests are now passing. Keith Packard (5): hw/rx: Allow execution without either bios or kernel target/rx: Set exception vector base to 0xff80 target/rx:

[PATCH 5/5] target/rx: Remove TCG_CALL_NO_WG from helpers which write env

. Signed-off-by: Keith Packard --- target/rx/helper.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/rx/helper.h b/target/rx/helper.h index ebb4739474..ac21f4fddd 100644 --- a/target/rx/helper.h +++ b/target/rx/helper.h @@ -13,18 +13,18

[PATCH 3/5] target/rx: Reset the CPU at qemu reset time

This ensure that the CPU gets reset every time QEMU resets. Signed-off-by: Keith Packard --- target/rx/cpu.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 37a6fdd569..04dd34b310 100644 --- a/target/rx/cpu.c +++ b/target

Re: Funny results with long double denorms on m68k

> When I developped the FPU emulation I compared the result of QEMU and a real > hardware using > https://github.com/vivier/m68k-testfloat and > https://github.com/vivier/m68k-softfloat It looks like the second of those has similar issues with m68k denorms? https://github.com/vivier/m68k-soft

Re: [PATCH] softfloat: Handle m68k extended precision denormals properly

> That does look like a correct change. I'll fold it in. > Please let us know if you encounter anything else. Thanks so much. With these fixes, all of my long double math library tests in picolibc are passing now (once I fixed a bunch of additional m68k-denorm related math library bugs). That in

Re: [PATCH] softfloat: Handle m68k extended precision denormals properly

001 0x8000 0x I think the enclosed additional patch fixes this. I've still got 75 fmal failures on this target, but the obvious 'multiply is broken' problem appears fixed. From b722c92f8329f56f5243496eca3779f1156aff4f Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Su

Funny results with long double denorms on m68k

I'm doing some testing of an fmal implementation and discovered some "odd" results on m68k where the emulated 80-bit FPU is generating results that don't match how GCC computes things. Assuming gcc is correct, this means there are some subtle bugs in how qemu is handling denorms for this platform.

[PATCH] target/m68k: Map FPU exceptions to FPSR register

Add helpers for reading/writing the 68881 FPSR register so that changes in floating point exception state can be seen by the application. Call these helpers in pre_load/post_load hooks to synchronize exception state. Signed-off-by: Keith Packard --- target/m68k/cpu.c| 12

Re: [PATCH] target/m68k: Map FPU exceptions to FPSR register

> Good catch. Mostly ok. Thanks much for looking at this. > No need for inline markers. Thanks. > In general it is bad form to call HELPER(foo) directly. In this case > it doesn't hurt, but better form to reverse the implementations. Good point. I had copied this from the arm vfp code which

[PATCH] target/m68k: Map FPU exceptions to FPSR register

Add helpers for reading/writing the 68881 FPSR register so that changes in floating point exception state can be seen by the application. Signed-off-by: Keith Packard --- target/m68k/cpu.h| 2 ++ target/m68k/fpu_helper.c | 72 target/m68k

[PATCH 0/3] target/m68k: Fix a few semihosting bugs

The first two patches mirror similar patches I recently sent for nios2. 1. Use correct parameter for EXIT (d1 instead of d0) 2. Fix use of deposit64 in LSEEK (argument order was incorrect) The second patch has also been submitted by Peter Maydell, it's included here because it was required to g

[PATCH 1/3] target/m68k: Pass semihosting arg to exit

Instead of using d0 (the semihost function number), use d1 (the provide exit status). Signed-off-by: Keith Packard --- target/m68k/m68k-semi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 88ad9ba814..12235759c7

[PATCH 3/3] target/m68k: Support semihosting on non-ColdFire targets

pport for non-CodeFire processors by matching BKPT #0 instructions. When semihosting is disabled, convert those back to illegal op exceptions. Signed-off-by: Keith Packard --- target/m68k/cpu.h | 1 + target/m68k/op_helper.c | 16 target/m68k/translate.c | 4 3 files c

[PATCH 2/3] target/m68k: Fix semihost lseek offset computation

The arguments for deposit64 are (value, start, length, fieldval); this appears to have thought they were (value, fieldval, start, length). Reorder the parameters to match the actual function. Signed-off-by: Keith Packard --- target/m68k/m68k-semi.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH] target/nios2: Pass semihosting arg to exit

> Yeah, the closest to a "standard" we have for nios2 is that > I asked the Codesourcery folks to document it in the libgloss > sources and put the URL to it in a comment at the top of > nios2-semi.c, given that there's no official spec and the > original and main guest-side user is libgloss. > m6

[PATCH] target/nios2: Pass semihosting arg to exit

Instead of using R_ARG0 (the semihost function number), use R_ARG1 (the provided exit status). Signed-off-by: Keith Packard --- target/nios2/nios2-semi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index

Re: [PATCH] target/nios2: Pass semihosting arg to exit

> says that for HOSTED_EXIT the exit code is in r5, > not in a parameter block pointed to by r5. That > would imply that the correct change is to use > R_ARG1 rather than R_ARG0 here. Ah, thanks -- I hadn't managed to find the actual standard yet. I'll resubmit with that fixed. -- -keith sign

[PATCH] target/nios2: Fix semihost lseek offset computation

The arguments for deposit64 are (value, start, length, fieldval); this appears to have thought they were (value, fieldval, start, length). Reorder the parameters to match the actual function. Signed-off-by: Keith Packard --- target/nios2/nios2-semi.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH] target/nios2: Pass semihosting arg to exit

Instead of using the function number (which is always zero), fetch the application-provided exit code argument and pass that to the two exit functions. Signed-off-by: Keith Packard --- target/nios2/nios2-semi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target

[PATCH] semihosting: Write back semihosting data before completion callback

and potentially fix bugs in other cases. Signed-off-by: Keith Packard --- semihosting/syscalls.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c index 508a0ad88c..78ba97d7ab 100644 --- a/semihosting/syscalls

Re: [PATCH] tcg: Remove dh_alias indirection for dh_typecode

Richard Henderson writes: > Reported-by: Keith Packard > Signed-off-by: Richard Henderson Looks good to me, and it passes my very simple test when run on s390. Tested-by: Keith Packard -- -keith signature.asc Description: PGP signature

Re: [PATCH] tcg: Add 'signed' bit to typecodes

Richard Henderson writes: > The signed information is still there, merged with the typecode: > > #define dh_typecode_void 0 > #define dh_typecode_noreturn 0 > #define dh_typecode_i32 2 > #define dh_typecode_s32 3 > #define dh_typecode_i64 4 > #define dh_typecode_s64 5 > #define dh_typecode_ptr 6

[PATCH] tcg: Add 'signed' bit to typecodes

n -5 quo 0 The correct result is: num -9 den -5 quo 1 This issue was originally discovered when running snek on s390x under qemu 6.2: https://github.com/keith-packard/snek/issues/58 Signed-off-by: Keith Packard --- include/exec/helper-head.h | 25 ++---

Re: [PATCH v2 4/4] tests/tcg: add HeapInfo checking to semihosting test

Alex Bennée writes: > +asprintf(&heap_info, "heap: %p -> %p\n", info.heap_base, > info.heap_limit); > +__semi_call(SYS_WRITE0, (uintptr_t) heap_info); > +if (info.heap_base != brk) { That requires qemu to know a lot about the run-time environment, which it rarely does in my experien

Re: [PATCH v2 2/4] semihosting/arm-compat-semi: unify GET/SET_ARG helpers

Alex Bennée writes: > Note: we aren't currently testing riscv32 due to missing toolchain for > check-tcg tests. That's surprising -- the usual risc-v toolchain supports both 64- and 32- bit targets. Othewise, this patch is Reviewed-by: Keith Packard -- -keith signature

Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO

Alistair Francis writes: > I have started on the effort, but I have not finished yet. Adding > riscv_cpu_is_32bit() was the first step there and I have some more > patches locally but I don't have anything working yet. That's awesome. I think waiting until we see what APIs you're developing for

Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO

Peter Maydell writes: > ILP32 for AArch64 is a zombie target -- it is kinda-sorta > supported in some toolchains but has no support in eg > the Linux syscall ABI. The semihosting ABI does not implement > any kind of ILP32 variant -- you can have A32/T32 (AArch32) > semihosting, where register and

Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO

Peter Maydell writes: > For semihosting for Arm what matters is "what state is the core > in at the point where it makes the semihosting SVC/HLT/etc insn?". Ok, that means we *aren't* talking about -mabi=ilp32, which is good -- in my current picolibc implementation, the semihosting code uses a p

Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO

Peter Maydell writes: > Also, you don't seem to have the correct "is the CPU in > 32-bit or 64-bit mode" test here: you cannot rely on target_ulong > being the right size, you must make a runtime check. Do you mean whether a dual aarch64/arm core is in arm or aarch64 mode, or whether an aarch64

Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO

Alex Bennée writes: > I'm not sure this every worked properly and it's certainly not > exercised by check-tcg or Peter's semihosting tests. Hoist it into > it's own helper function and attempt to validate the results in the > linux-user semihosting test at the least. The patch is mostly code mot

[PATCH] Create API for checking and clearing GDB connection status

ONFIG_USER_ONLY. This avoids a segfault when qemu is run with the '-s' flag (create a gdb protocol socket), but without the '-S' flag (delay until 'c' command is received). Signed-off-by: Keith Packard --- gdbstub.c | 51 +

Re: [PATCH] gdbstub.c uses incorrect check for active gdb in use_gdb_syscalls

Alex Bennée writes: > It would be better to wrap the test in a function (static bool > is_connected()?) so the semantic meaning is clear in the code and we can > fix things in one place if needed. That makes good sense to me. > How exactly did you create the segfault? Just starting with -s and

Re: [PATCH v1 16/20] riscv: Add semihosting support

Alistair Francis writes: > Whoops, I thought I had already reviewed this commit. You had provided quite extensive review with lots of useful comments, but never added the magic tag for this commit :-) -- -keith signature.asc Description: PGP signature

[PATCH 6/9] riscv: Add semihosting support for user mode

From: Kito Cheng This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng Reviewed-by: Keith Packard Message-Id: <20201214200713.3886611-7-

[PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState *

es on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis v2: Add common_semi_rambase hook to get memory address for SYS_HEAPINFO call.

[PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set

env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard Message

[PATCH 2/9] semihosting: Change common-semi API to be architecture-independent

-by: Keith Packard Reviewed-by: Alistair Francis Message-Id: <20201214200713.3886611-3-kei...@keithp.com> --- hw/semihosting/common-semi.c | 16 ++-- hw/semihosting/common-semi.h | 36 +++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-us

[PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pd

[PATCH 8/9] semihosting: Implement SYS_TMPNAM

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-9-kei...@keithp.com> --- hw/semihosting/common-semi.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-

[PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ

These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-8-kei...@keithp.com> --- hw/semihosting/common-semi.c | 16 include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 3

[PATCH 9/9] semihosting: Implement SYS_ISERROR

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-10-kei...@keithp.com> --- hw/semihosting/common-semi.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-

[PATCH 1/9] semihosting: Move ARM semihosting code to shared directories

riable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis v2 Place common-semi.c name in arm_ss, just

[PATCH 5/9] riscv: Add semihosting support

Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-6-

[PATCH] gdbstub.c uses incorrect check for active gdb in use_gdb_syscalls

this check or whether it should check each time it is called to see if a gdb connection is currently acive. For the second question, I don't have a clear idea; mixing gdb and native calls seems problematic for stateful operations like file open/close. Signed-off-by: Keith Packard --- gd

[PATCH 9/9] semihosting: Implement SYS_ISERROR

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b0648c3812..abc15bf219 100644 --- a/hw/semihosting

[PATCH 1/9] semihosting: Move ARM semihosting code to shared directories

riable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis v2 Place common-semi.c name in arm_ss, just

[PATCH 5/9] riscv: Add semihosting support

Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is

[PATCH 8/9] semihosting: Implement SYS_TMPNAM

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b1368d945c

[PATCH 2/9] semihosting: Change common-semi API to be architecture-independent

-by: Keith Packard Reviewed-by: Alistair Francis --- hw/semihosting/common-semi.c | 16 ++-- hw/semihosting/common-semi.h | 36 +++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8

[PATCH 6/9] riscv: Add semihosting support for user mode

From: Kito Cheng This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng Reviewed-by: Keith Packard --- linux-user/riscv/cpu_loop.c | 5

[PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ

These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 16 include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 3 files changed, 22 insertions(+) diff --git a/hw/semihosting

[PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set

env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard ---

[PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState *

es on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis v2: Add common_semi_rambase hook to get memory address for

[PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

. Change internal semihosting interfaces 4. Fix SYS_HEAPINFO crash on ARM 5-6. Add RISC-V semihosting implementation 7-9. Add missing semihosting operations from release 2.0 Signed-off-by: Keith Packard

Re: [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

Alex Bennée writes: > Hmm scratch that... it fails in a number of linux-user only builds with: > > /usr/bin/ld: > libqemu-aarch64_be-linux-user.fa.p/linux-user_aarch64_cpu_loop.c.o: in > function `cpu_loop': > /builds/stsquad/qemu/build/../linux-user/aarch64/cpu_loop.c:133: undefined > ref

Re: [PATCH 5/8] riscv: Add semihosting support [v13]

at applies cleanly on top of the rest of my series, so I think we can just leave it like that unless someone wants it presented differently. Not sure why I thought this was working before; I clearly missed the most important bit. Reviewed-by: Keith Packard I've got a github repo with these bi

Re: [PATCH 5/8] riscv: Add semihosting support [v13]

Kito Cheng writes: > Hi Keith: > > Thanks for the patch, I've verified with newlib semihosting support > which is contributed by Craig Blackmore from embecosm, > and I would like to add semihosting to user mode, do you mind add this > patch into this patch series? I tried to add that already, bu

[PATCH 4/8] semihosting: Support SYS_HEAPINFO when env->boot_info is not set

env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard --- hw/semihost

[PATCH 6/8] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ

These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 16 include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 3 files changed, 22 insertions(+) diff --git a/hw/semihosting

[PATCH 8/8] semihosting: Implement SYS_ISERROR

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 9a04d98e4e..fda0e714ef 100644 --- a/hw/semihosting

[PATCH 7/8] semihosting: Implement SYS_TMPNAM

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index c84b0d906b

[PATCH 5/8] riscv: Add semihosting support [v13]

Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is

[PATCH 3/8] semihosting: Change internal common-semi interfaces to use CPUState * [v2]

es on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis v2: Add common_semi_rambase hook to get memory address for

[PATCH 1/8] semihosting: Move ARM semihosting code to shared directories [v3]

riable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis v2 Place common-semi.c name in arm_ss, just

[PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

. Change internal semihosting interfaces 4. Fix SYS_HEAPINFO crash on ARM 5. Add RISC-V semihosting implementation 6-8. Add missing semihosting operations from release 2.0 Signed-off-by: Keith Packard

[PATCH 2/8] semihosting: Change common-semi API to be architecture-independent

-by: Keith Packard Reviewed-by: Alistair Francis --- hw/semihosting/common-semi.c | 16 ++-- hw/semihosting/common-semi.h | 36 +++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8

Re: [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *

Alistair Francis writes: > I'm not sure common is the right name here, as it is really just ARM > and RISC-V, but I don't have a better name to use. We've already seen some interest for other architectures; Benjamin Herrenschmidt was looking at using this for PPC, for instance. He got stuck at t

Re: [PATCH 4/4] riscv: Add semihosting support [v11]

o send out a new version here. Sorry! From a6cb1a52a6c2404a9bdc22bb5e00bccb65ab0730 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 26 Oct 2020 12:20:01 -0700 Subject: [PATCH 4/4] riscv: Add semihosting support [v12] Adapt the arm semihosting support code for RISCV. This implementation is

Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories [v3]

Alistair Francis writes: > Reviewed-by: Alistair Francis Thanks much. I think we'll need some help getting the next two patches reviewed; that touches ARM code. The last patch is also RISC-V only. -- -keith signature.asc Description: PGP signature

[PATCH] semihosting: Merge semihosting console init functions to fix READC

did before the referenced commit was applied. Signed-off-by: Keith Packard --- hw/semihosting/config.c | 21 ++- hw/semihosting/console.c | 58 ++- include/hw/semihosting/semihost.h | 4 +-- softmmu/vl.c | 5 +-- 4 fil

Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories

Alex Bennée writes: > specific_ss.add(when: 'CONFIG_ARM_STYLE_SEMIHOSTING', > if_true: files ('common-semi.c')) I've sent another version of the series using this plan. It does look a bit nicer as the only changes required when adding support to another target is to place thi

[PATCH 4/4] riscv: Add semihosting support [v11]

Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is

[PATCH 2/4] semihosting: Change common-semi API to be architecture-independent

-by: Keith Packard --- hw/semihosting/common-semi.c | 16 ++-- hw/semihosting/common-semi.h | 36 +++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8 target/arm/helper.c

[PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *

e of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 326 ++--

[PATCH 0/4] Add RISC-V semihosting support

This series adapts the existing ARM semihosting code to be target-independent, and then uses that to provide semihosting support for RISC-V targets.

[PATCH 1/4] semihosting: Move ARM semihosting code to shared directories [v3]

riable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard v2 Place common-semi.c name in arm_ss, just as arm-semi.c was v3

Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories

Alex Bennée writes: > I don't think we want arm specific adds in the common code. I think what > Peter was suggesting is a new config symbol that only ARM and RISC > define, e.g something like: > > specific_ss.add(when: 'CONFIG_ARM_STYLE_SEMIHOSTING', > if_true: files ('common

Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories

Peter Maydell writes: >> arm_ss.add(when: 'CONFIG_TCG', if_true: files ('common-semi.c')) >> riscv_ss.add(files('common-semi.c')) >> >> This appears to work in my testing (building arm, risc-v and x86_64 >> configs). > > I'm not a kconfig expert but it might be preferable to have

Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories

Peter Maydell writes: >> +specific_ss.add(when: 'CONFIG_TCG', if_true: files ('common-semi.c')) > > I think this adds this file to the compilation for all TCG targets; > you only want it for targets which have Arm-semihosting-ABI compatible > semihosting. (Various other targets either don't have

[PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *

e of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 326 ++--

[PATCH 1/4] semihosting: Move ARM semihosting code to shared directories

e, but the contents of the two files are unchanged. Signed-off-by: Keith Packard --- target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 hw/semihosting/meson.build| 2 ++ linux-user/arm/meson.build| 3 --- linux-user/me

[PATCH 2/4] semihosting: Change common-semi API to be architecture-independent

-by: Keith Packard --- hw/semihosting/common-semi.c | 16 ++-- hw/semihosting/common-semi.h | 36 +++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8 target/arm/helper.c

[PATCH 0/4] riscv: Add semihosting support [v10]

This series first adapts the existing ARM semihosting code to be architecture-neutral, then adds RISC-V semihosting support using that. Patch 1/4 moves the ARM semihosting support code to common directories and adapts the build system to match. Patch 2/4 changes the public API to this code to use

[PATCH 4/4] riscv: Add semihosting support [v10]

Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is

Re: [PATCH] riscv: Add semihosting support [v8]

Richard Henderson writes: > On 10/23/20 2:49 PM, Keith Packard via wrote: >> static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) >> { >> -generate_exception(ctx, RISCV_EXCP_BREAKPOINT); >> +uint32_t pre= opcode_at(&ctx->base, ctx->base.

Re: [PATCH] riscv: Add semihosting support [v8]

Richard Henderson writes: > This is no different to EXCP_DEBUG, really, which is also internal to qemu but > user-visible in the same way. Just adjust the logging in > riscv_cpu_do_interrupt. I think that's already handled by the early return in riscv_cpu_do_interrupt after handling the RISCV_

Re: [PATCH 1/2] riscv: Add sifive test device to sifive_e target

Alistair Francis writes: > The sifive_u and sifive_e model real hardware (the names are confusing > I agree) so I would rather not add a virtual device. That seems reasonable; semihosting will be a much better solution for the long term anyways. I posted this because we've been maintaining it ou

  1   2   >