Peter's v2 already includes the fixup (update #6)
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https://bugs.launchpad.net/bugs/1879587
Title:
Register number in ESR is incorrect for certain banked registers when
switching from
It seems like this is your patch plus my fixup so this is good to me and
already tested locally. Thanks again.
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Title:
Register number in ESR is
pping code doesn't seem quite right. Applying this patch (on
top of yours):
>From e2182581dcdeedc2cb88cd21b88b4db744677737 Mon Sep 17 00:00:00 2001
From: Julien Freche
Date: Tue, 4 Aug 2020 11:54:49 -0700
Subject: [PATCH] Possible fix
---
target/arm/helper.c | 11 +--
1 file changed,
Of course. I just tested the patch (used the branch from
https://github.com/patchew-project/qemu) and it didn't seem to help.
Could that be linked to the fact that the translation is only in the SMC
exception path? It should probably target the MSR exception path also
(and probably others too). It'
Maybe it's covered by EXCP_HYP_TRAP already...
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Title:
Register number in ESR is incorrect for certain banked registers when
switching from AA
This is with qemu-system-aarch64 - forgot to mention it explicitly. So,
it will only affect qemu for ARM 64-bit.
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Title:
Register number in ESR
Public bug reported:
I am running into a situation where I have:
- A hypervisor running in EL2, AA64
- A guest running in EL1, AA32
We trap certain accesses to special registers such as DACR (via
HCR.TVM). One instruction that is trapped is:
ee03ef10 ->mcr 15, 0, lr, cr3, cr0, {0}
The
Makes sense. Debugging is on me then :) Both patches behave as expected,
thanks!
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https://bugs.launchpad.net/bugs/1863685
Title:
ARM: HCR.TSW traps are not implemented
Status in QEMU:
Sorry, I meant the operation is a write (TVM is on). The result of the
operation is setting DACR to 0 so the guest stops progressing after
that.
Anyway, since the issue could also be on my side, I don't want to block
you with this.
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Thanks for the quick turn around! I tested both your patches together
(it's useful to have both to emulate set/way flushing inside a guest)
and I am getting something unexpected. At some point, we are trapping on
an access to DACR but ESR_EL2 doesn't seem to make a lot of sense:
0xfe00dc0. I am run
Thank you! I also tested AArch32 and the code works. Ship it!
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https://bugs.launchpad.net/bugs/1855072
Title:
ARM: HCR.TVM traps are not implemented
Status in QEMU:
In Progress
Bug
Public bug reported:
On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap
data or unified cache maintenance instructions that operate by Set/Way."
Quoting the ARM manual:
If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped
to EL2, reported using EC
I tested in AArch64 mode and it worked for me. Looking at the patch, we
might be missing trapping for "TTBCR"in AA32 though.
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Title:
ARM: HCR.TV
Thank you for the patch! I am happy to test this for you. I will apply
the patch/compile/test and get back to you.
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Title:
ARM: HCR.TVM traps ar
Public bug reported:
On AARCH64, setting HCR.TVM to 1 is supposed to trap all writes to
CTLR_EL1, TTBR0_EL1, TTBR1_EL1, TCR_EL1, ESR_EL1, FAR_EL1, AFSR0_EL1,
AFSR1_EL1, MAIR_EL1, AMAIR_EL1, and CONTEXTIDR_EL1. However, it
currently has no effect (QEMU emulator version 4.1.1).
It is also likely th
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