On Wed, Aug 16, 2023 at 5:57 AM Richard Henderson
wrote:
>
> This may or may not improve performance.
> It appears to result in slightly larger code,
> but perhaps not enough to matter.
I have collected some power9 macro performance data for an smp compile workload:
Setup
-
- Power9 powernv
On Wed, 16 Aug 2023, 5:57 am Richard Henderson, <
richard.hender...@linaro.org> wrote:
> With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIP.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 25 ++---
> 1 file changed, 22 insertions(+), 3
On 16/8/23 2:07 am, Richard Henderson wrote:
On 8/14/23 22:01, Jordan Niethe wrote:
Direct branch patching was disabled when using TCG_REG_TB in commit
736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation"). Commit
7502f89c74 ("tcg/ppc: Use prefixed instructions for
irectly to a translation block the setup sequence can
be skipped if the caller sets up TCG_REG_TB as there is no possible race
in this case.
Signed-off-by: Jordan Niethe
---
This is just a proof of concept, not sure that this is the correct way
to do this or even if it is something we'd like
offset(s, which);
> }
>
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> --
> 2.34.1
>
Thank you for implementing this Richard.
I was able to boot mttcg guests on P9 and P10 hosts.
Tested-by: Jordan Niethe
Reviewed-by: Jordan Niethe
On Sat, Aug 5, 2023 at 7:34 AM Richard Henderson
wrote:
>
> When a direct branch is out of range, we can load the destination for
> the indirect branch using PLA (for 16GB worth of buffer) and PLD from
> the TranslationBlock for everything larger.
>
> This means the patch affects exactly one instr
mp = tcg_pcrel_diff(s, (void *)arg) - tmp;
> +if (tmp == sextract64(tmp, 0, 34)) {
> +/* pla ret,value = paddi ret,0,value,1 */
> +tcg_out_mls_d(s, ADDI, ret, 0, tmp, 1);
> +return;
> +}
> +}
> +
> /* Load 32-bit immediates with two insns. Note that we've already
> eliminated bare ADDIS, so we know both insns are required. */
> if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
> --
> 2.34.1
>
Reviewed-by: Jordan Niethe
+tcg_out_8ls_d(s, PSTXSD, rt & 31, base, offset, 0);
> +return;
> +case LXV:
> +tcg_out_8ls_d(s, PLXV, rt & 31, base, offset, 0);
> +return;
> + case STXV:
> +tcg_out_8ls_d(s, PSTXV, rt & 31, base, offset, 0);
> +return;
> +}
> +}
> +
> /* For unaligned, or very large offsets, use the indexed form. */
> if (offset & align || offset != (int32_t)offset || opi == 0) {
> if (rs == base) {
> --
> 2.34.1
>
Reviewed-by: Jordan Niethe
On 5/4/23 1:04 am, Richard Henderson wrote:
Something is wrong with this code, and also wrong with gdb on the
sparc systems to which I have access, so I cannot debug it either.
Disable for now, so the release is not broken.
I'm not sure if it is the entire problem but it looks like the broke
qemu/-/issues/1726
Fixes: 20b6643324 ("tcg/ppc: Reorg goto_tb implementation")
Reported-by: Anushree Mathur
Co-developed-by: Benjamin Gray
Signed-off-by: Jordan Niethe
---
tcg/ppc/tcg-target.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg
On Mon, Jul 17, 2023 at 11:24 AM Jordan Niethe wrote:
[snip]
>
> Reported-by: Anushree Mathur
> Co-developed-by: Benjamin Gray
> Signed-off-by: Jordan Niethe
Sorry, should also have:
Signed-off-by: Benjamin Gray
[snip]
o_tb implementation")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1726
Reported-by: Anushree Mathur
Tested-by: Anushree Mathur
Tested-by: Michael Tokarev
Reviewed-by: Richard Henderson
Co-developed-by: Benjamin Gray
Signed-off-by: Jordan Niethe
Signed-off-by: Benjamin Gray
---
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