On Mon, 29 Sep 2025 14:36:23 +0100
Shameer Kolothum wrote:
> For accelerated SMMUv3, we need nested parent domain creation. Add the
> callback support so that VFIO can create a nested parent.
>
> In the accelerated SMMUv3 case, the host SMMUv3 is configured in nested
> mode (S1 + S2), and the gu
On Mon, 29 Sep 2025 14:36:42 +0100
Shameer Kolothum wrote:
> From: Yi Liu
>
> If user wants to expose PASID capability in vIOMMU, then VFIO would also
> report the PASID cap for this device if the underlying hardware supports
> it as well.
>
> As a start, this chooses to put the vPASID cap in
On Mon, 29 Sep 2025 14:36:31 +0100
Shameer Kolothum wrote:
> From: Eric Auger
>
> At the moment we do not support other function than function 0. So according
> to ACPI spec "_DSM (Device Specific Method)" description, bit 0 should rather
> be 0, meaning no other function is supported than func
On Thu, 2 Oct 2025 08:03:09 +
Shameer Kolothum wrote:
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: 01 October 2025 14:58
> > To: Shameer Kolothum
> > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> > eric.au...@redhat.com; peter.mayd...@linaro.org; Jason Gunthorpe
>
On Thu, 2 Oct 2025 07:37:46 +
Shameer Kolothum wrote:
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: 01 October 2025 13:56
> > To: Shameer Kolothum
> > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> > eric.au...@redhat.com; peter.mayd...@linaro.org; Jason Gunthorpe
>
On Wed, 1 Oct 2025 19:36:47 +0200
Eric Auger wrote:
> Hi Shameer,
>
> On 9/29/25 3:36 PM, Shameer Kolothum wrote:
> > For accelerated SMMUv3, we need nested parent domain creation. Add the
> > callback support so that VFIO can create a nested parent.
> >
> > In the accelerated SMMUv3 case, the h
On Mon, 29 Sep 2025 14:36:37 +0100
Shameer Kolothum wrote:
> Currently QEMU SMMUv3 has RIL support by default. But if accelerated mode
> is enabled, RIL has to be compatible with host SMMUv3 support.
>
> Add a property so that the user can specify this.
>
> Signed-off-by: Shameer Kolothum
One
On Mon, 29 Sep 2025 14:36:41 +0100
Shameer Kolothum wrote:
> Subsequent patch will make use of this to add a PASID CAP for assigned
> devices.
>
> Signed-off-by: Shameer Kolothum
Trivial stuff.
> ---
> backends/iommufd.c | 9 +
> include/system/host_iommu_device.h |
On Mon, 29 Sep 2025 14:36:40 +0100
Shameer Kolothum wrote:
Bring the bit of the description in the title down here as well.
Depending on what tools people use for browsing git it might
end up in very different places on their screen.
> And store it in HostIOMMUDeviceCaps for later use.
>
> Sign
On Fri, 19 Sep 2025 16:33:12 +0530
Arpit Kumar wrote:
> On 17/09/25 04:55PM, Jonathan Cameron wrote:
> >On Tue, 16 Sep 2025 13:37:35 +0530
> >Arpit Kumar wrote:
> >
> >> -Storing physical ports info during enumeration.
> >> -Refactored changes using physical ports info for
> >> Identify Switc
On Mon, 29 Sep 2025 14:36:28 +0100
Shameer Kolothum wrote:
> Here we return the IOMMU address space if the device has S1 translation
> enabled by Guest. Otherwise return system address space.
>
> Signed-off-by: Shameer Kolothum
> Signed-off-by: Shameer Kolothum
Naming question inline.
> ---
>
On Mon, 29 Sep 2025 14:36:26 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Allocate and associate a vDEVICE object for the Guest device with the
> vIOMMU. This will help the host kernel to make a virtual SID --> physical
> SID mapping. Since we pass the raw invalidation commands(eg: CM
On Mon, 29 Sep 2025 14:36:24 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -If found an existing viommu reuse that.
> -Else,
> Allocate a vIOMMU with the nested parent S2 hwpt allocated by VFIO.
> Though, iommufd’s vIOMMU model support
On Mon, 29 Sep 2025 14:36:20 +0100
Shameer Kolothum wrote:
Space between : and Make
I'd repeat the patch title bit of the sentence in here just to make
it more readable.
> And set to the current default smmu_ops. No functional change intended.
> This will allow SMMUv3 accel implementation to set
From: Shiju Jose
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands
On Mon, 8 Sep 2025 18:52:11 +0530
Arpit Kumar wrote:
> On 05/09/25 05:12PM, Jonathan Cameron wrote:
> >On Thu, 4 Sep 2025 18:49:02 +0530
> >Arpit Kumar wrote:
> >
> >> This patch series refactor existing support for Identify Switch Device
> >> and Get Physical Port State by utilizing physical
On Thu, 10 Jul 2025 14:26:07 +0100
Peter Maydell wrote:
> On Wed, 14 May 2025 at 12:50, Michael S. Tsirkin wrote:
> >
> > From: Vinayak Holikatti
> >
> > CXL spec 3.2 section 8.2.10.9.5.3 describes media operations commands.
> > CXL devices supports media operations discovery command.
> >
> > S
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error C
From: Shiju Jose
Refactor CXL event injection to use struct for common command
arguments.
Suggested-by: Markus Armbruster
Signed-off-by: Shiju Jose
Signed-off-by: Jonathan Cameron
---
qapi/cxl.json | 89 +--
1 file changed, 58 insertions(+), 31
On Thu, 7 Aug 2025 19:10:37 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> This creates a specific CXL host bridge (0001:00) with four cxl
> root ports on sbsa-ref. And the memory layout provides separate
> space windows for the cxl host bridge in the sbsa-ref memmap:
>
> - 64K CXL Host Brid
On Thu, 7 Aug 2025 18:59:10 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> Define a new CXL host bridge type (TYPE_CXL_HOST). This is an
> independent CXL host bridge which combined GPEX features (ECAM, MMIO
> windows and irq) and CXL Host Bridge Component Registers (CHBCR).
>
> The root bus
On Thu, 7 Aug 2025 18:59:09 +0800
wangyuquan wrote:
> This renames some descriptions and definitions of pxb cxl host
> bridge, since the original names can be confusing.
>
> Signed-off-by: Yuquan Wang
This is fine with me - sorry for my lack of attention on this series.
I'm not set up to test
On Wed, 17 Sep 2025 21:56:25 +0900
Akihiko Odaki wrote:
> Make AddressSpaces QOM objects to ensure that they are destroyed when
> their owners are finalized and also to get a unique path for debugging
> output.
>
> The name arguments were used to distinguish AddresSpaces in debugging
> output, b
On Tue, 16 Sep 2025 13:37:36 +0530
Arpit Kumar wrote:
> -added assert-deassert PERST implementation
> for physical ports (both USP and DSP's).
> -assert PERST involves bg operation for holding 100ms.
> -reset PPB implementation for physical ports.
>
> Signed-off-by: Arpit Kumar
> @@ -4702,11
From: Shiju Jose
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature() to the local scope where they are used.
Signed-off-by: Shiju Jose
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 17 +++--
1 file changed, 7 insertions(+), 10
These two features have been used in testing the related EDAC RAS
features drivers in Linux which are now upstream. Only minor tweaks
from the second part of:
https://lore.kernel.org/qemu-devel/20250811085530.2263-1-shiju.j...@huawei.com/
[PATCH v6 0/8] hw/cxl: Update CXL events to rev3.2 and add m
From: Shiju Jose
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The
subclasses for this operation vary in terms of the scope of the sparing
being performed. The Cacheline sparing subclass refers to a sparing
a
On Tue, 16 Sep 2025 13:37:36 +0530
Arpit Kumar wrote:
> -added assert-deassert PERST implementation
> for physical ports (both USP and DSP's).
> -assert PERST involves bg operation for holding 100ms.
> -reset PPB implementation for physical ports.
>
> Signed-off-by: Arpit Kumar
See below for w
On Tue, 16 Sep 2025 13:37:35 +0530
Arpit Kumar wrote:
> -Storing physical ports info during enumeration.
> -Refactored changes using physical ports info for
> Identify Switch Device (Opcode 5100h) & Get Physical Port State
> (Opcode 5101h) physical switch FM-API command set.
>
> Signed-off-by:
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command t
From: Davidlohr Bueso
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the reque
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in
Hi Michael,
This is the 1st CXL set that I think is ready for upstream.
They are lightly tweaked and rebased from the first part of:
https://lore.kernel.org/qemu-devel/20250811085530.2263-1-shiju.j...@huawei.com/
[PATCH v6 0/8] hw/cxl: Update CXL events to rev3.2 and add maintenance support
for m
On Wed, 17 Sep 2025 13:51:58 +0200
Markus Armbruster wrote:
> Functions that use an Error **errp parameter to return errors should
> not also report them to the user, because reporting is the caller's
> job. When the caller does, the error is reported twice. When it
> doesn't (because it recove
On Mon, 15 Sep 2025 15:19:38 +0800
Bibo Mao wrote:
> On LoongArch Virt Machine, MMIO region with GPEX host bridge is
> 0x4000 -- 0x7FFF. The total size is 1G bytes and it is enough
> for emulated virtio devices basically.
>
> However on some conditions such as hostmem is added with virti
On Tue, 9 Sep 2025 14:32:57 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This header contains the transport encoding for an SPDM message that
> uses the SPDM over Storage transport as defined by the DMTF DSP0286.
>
> Signed-off-by: Wilfred Mallawa
> ---
> include/system/spdm-soc
On Tue, 9 Sep 2025 14:32:58 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> Adds the NVMe Admin Security Send/Receive command support with support
> for DMTFs SPDM. The transport binding for SPDM is defined in the
> DMTF DSP0286.
>
> Signed-off-by: Wilfred Mallawa
> Reviewed-by: Ste
On Tue, 9 Sep 2025 14:33:00 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This patch extends the existing support we have for NVMe with only DoE
> to also add support to SPDM over the NVMe Security Send/Recv commands.
>
> With the new definition of the `spdm-trans` argument, users
On Mon, 8 Sep 2025 19:18:56 +0530
Arpit Kumar wrote:
> On 05/09/25 04:59PM, Jonathan Cameron wrote:
> >On Thu, 4 Sep 2025 18:49:03 +0530
> >Arpit Kumar wrote:
> >
> >> -Storing physical ports info during enumeration.
> >> -Refactored changes using physical ports info for
> >> Identify Switch
On Tue, 9 Sep 2025 14:32:59 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> SPDM maybe used over different transports. This patch specifies the
> trasnport types as an enum with a qdev property definition such that
> a user input transport type (string) can be mapped directly into the
On Tue, 9 Sep 2025 14:32:56 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This is to support uni-directional transports such as SPDM over Storage.
> As specified by the DMTF DSP0286.
>
> Also update spdm_socket_rsp() to use the new send()/receive() functions. For
> the case of spdm
On Thu, 4 Sep 2025 18:49:02 +0530
Arpit Kumar wrote:
> This patch series refactor existing support for Identify Switch Device
> and Get Physical Port State by utilizing physical ports (USP & DSP)
> information stored during enumeration.
>
> Additionally, it introduces new support for Physical
On Thu, 4 Sep 2025 18:49:03 +0530
Arpit Kumar wrote:
> -Storing physical ports info during enumeration.
> -Refactored changes using physical ports info for
> Identify Switch Device (Opcode 5100h) & Get Physical Port State
> (Opcode 5101h) physical switch FM-API command set.
>
> Signed-off-by:
On Thu, 4 Sep 2025 13:10:58 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> SPDM maybe used over different transports, such as PCIe Data Object
> Exchange (DoE) or Storage amongst others. This patch
Odd line wrap. I'd also drop the 'amongst others' as 'such as' already
suggests ther
On Thu, 4 Sep 2025 13:10:59 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This patch extends the existing support we have for NVMe with only DoE
> to also add support to SPDM over the NVMe Security Send/Recv commands.
>
> With the new definition of the `spdm-trans` argument, users
On Thu, 4 Sep 2025 13:10:57 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> Adds the NVMe Admin Security Send/Receive command support with support
> for DMTFs SPDM. The transport binding for SPDM is defined in the
> DMTF DSP0286.
>
> Signed-off-by: Wilfred Mallawa
Hi Wilfred,
I ha
On Thu, 4 Sep 2025 13:10:55 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This is to support uni-directional transports such as SPDM over Storage.
> As specified by the DMTF DSP0286.
>
> Also update spdm_socket_rsp() to use the new send()/receive() functions. For
> the case of spdm
On Tue, 26 Aug 2025 15:46:30 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This patch extends the existing support we have for NVMe with only DoE
> to also add support to SPDM over the NVMe Security Send/Recv commands.
>
> With the new definition of the `spdm-trans` argument, users
On Tue, 26 Aug 2025 15:46:29 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> Adds the NVMe Admin Security Send/Receive command support with support
> for DMTFs SPDM. The transport binding for SPDM is defined in the
> DMTF DSP0286.
>
> Signed-off-by: Wilfred Mallawa
A few suggestions
On Tue, 26 Aug 2025 15:46:28 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
> This header contains the transport encoding for an SPDM message that
> uses the SPDM over Storage transport as defined by the DMTF DSP0286.
>
> Signed-off-by: Wilfred Mallawa
> ---
> include/system/spdm-soc
On Tue, 26 Aug 2025 15:46:27 +1000
Wilfred Mallawa wrote:
> From: Wilfred Mallawa
>
Hi Wilfred,
Great to see this support.
> This is to support uni-directional transports such as SPDM
> over Storage. As specified by the DMTF DSP0286.
Trivial, wrap commit closer to 75 chars.
>
> Signed-off-
On Thu, 14 Aug 2025 18:13:15 +0100
Peter Maydell wrote:
> Earlier this year, the Linux kernel's kernel-doc script was rewritten
> from the old Perl version into a shiny and hopefully more maintainable
> Python version. This commit series updates our copy of this script
> to the latest kernel vers
On Sun, 10 Aug 2025 20:34:05 -0700
Davidlohr Bueso wrote:
> Add basic plumbing for memory expander devices that support Back
> Invalidation. This introduces a 'hdm-db=on|off' parameter and
> exposes the relevant BI RT/Decoder component cachemem registers.
>
> Some noteworthy properties:
> - Dev
On Sun, 10 Aug 2025 20:34:02 -0700
Davidlohr Bueso wrote:
> As with the link speed and width training, have ad-hoc property for
> setting the flit mode and allow CXL components to make use of it.
>
> For the CXL root port and dsp cases, always report flit mode but
> the actual value after 'train
On Mon, 11 Aug 2025 09:55:30 +0100
wrote:
> From: Shiju Jose
>
> Memory sparing is defined as a repair function that replaces a portion of
> memory with a portion of functional memory at that same DPA. The
> subclasses for this operation vary in terms of the scope of the sparing
> being perform
On Mon, 11 Aug 2025 09:55:29 +0100
wrote:
> From: Davidlohr Bueso
>
> This adds initial support for the Maintenance command, specifically
> the soft and hard PPR operations on a dpa. The implementation allows
> to be executed at runtime, therefore semantically, data is retained
> and CXL.mem re
On Mon, 11 Aug 2025 09:55:23 +0100
wrote:
> From: Shiju Jose
>
> Refactor CXL event injection to use struct for common command
> arguments.
>
> Suggested-by: Markus Armbruster
> Signed-off-by: Shiju Jose
Very nice.
no tag as this will get my SoB anyway as I'll queue it up for
next cycle.
J
On Tue, 5 Aug 2025 22:57:05 -0700
Davidlohr Bueso wrote:
> As with the link speed and width training, have ad-hoc property for
> setting the flit mode and allow CXL components to make use of it.
>
> For the CXL root port and dsp cases, always report flit mode but
> the actual value after 'train
On Tue, 5 Aug 2025 22:57:07 -0700
Davidlohr Bueso wrote:
> Update the CFMW restrictions to also permit Back-Invalidate
> flows by default, which is aligned with the no-restrictions
> policy.
>
> While at it, document the 'restrictions=' option.
>
> Signed-off-by: Davidlohr Bueso
I sat on thi
On Tue, 5 Aug 2025 22:57:05 -0700
Davidlohr Bueso wrote:
> As with the link speed and width training, have ad-hoc property for
> setting the flit mode and allow CXL components to make use of it.
>
> For the CXL root port and dsp cases, always report flit mode but
> the actual value after 'train
On Thu, 7 Aug 2025 16:43:40 +0100
wrote:
> From: Shiju Jose
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in
On Fri, 8 Aug 2025 10:08:14 +0200
Markus Armbruster wrote:
> Functions that use an Error **errp parameter to return errors should
> not also report them to the user, because reporting is the caller's
> job. When the caller does, the error is reported twice. When it
> doesn't (because it recove
On Tue, 5 Aug 2025 22:23:00 +0800
peng guo wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU on a
> physical server, the 9p device fails to initialize properly. The kernel
> reports
> the following error:
>
> virtio: device uses modern interface but does not
On Mon, 4 Aug 2025 22:24:21 +0800
peng guo wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU on a
> physical server, the 9p device fails to initialize properly. The kernel
> reports
> the following error:
>
> virtio: device uses modern interface but does not
On Tue, 29 Jul 2025 09:54:39 -0700
Davidlohr Bueso wrote:
> Hello,
>
> The following allows support for component basic back invalidation discovery
> and config, by exposing the BI routing table and decoder registers. Instead
> of going the type2[1] route, this series proposes adding support for
On Wed, 30 Jul 2025 17:52:45 -0300
Fabiano Rosas wrote:
> Don't use the 'max' cpu for migration testing of aarch64. That cpu
> does not provide a stable set of features and is expected to break
> migration from time to time.
Whilst I can see the motivation, doesn't this leave us with a lack of
c
On Wed, 30 Jul 2025 15:21:41 +0300
Manos Pitsidianakis wrote:
> NVDIMM is used for fast rootfs with EROFS, for example by kata
> containers. To allow booting with static NVDIMM memory, add them to the
> device tree in arm virt machine.
>
> This allows users to boot directly with nvdimm memory de
On Sat, 26 Jul 2025 20:50:35 +0800
peng guo wrote:
> On Fri, Jul 25, 2025 at 02:53:37PM +0100, Jonathan Cameron wrote:
> > On Fri, 18 Jul 2025 21:35:45 +0800
> > peng guo wrote:
> >
> > > When using a CXL Type 3 device together with a virtio 9p device in QEMU,
> > > the
> > > 9p device fails
On Tue, 17 Jun 2025 12:06:49 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> Define a new CXL host bridge type (TYPE_CXL_HOST). This is an
> independent CXL host bridge which combined GPEX features (ECAM, MMIO
> windows and irq) and CXL Host Bridge Component Registers (CHBCR).
>
> The root bus
On Tue, 17 Jun 2025 12:06:48 +0800
wangyuquan wrote:
> This renames some descriptions and definitions of pxb cxl host
> bridge, since the original names can be confusing.
>
> Signed-off-by: Yuquan Wang
Fair enough.
Reviewed-by: Jonathan Cameron
> ---
> hw/pci-bridge/pci_expander_bridge.c | 8
On Tue, 17 Jun 2025 12:19:46 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> This creates a specific CXL host bridge (0001:00) with two cxl
> root ports on sbsa-ref. And the memory layout provides separate
> space windows for the cxl host bridge in the sbsa-ref memmap:
>
> - 64K CXL Host Brid
On Thu, 10 Jul 2025 20:13:38 +0530
Arpit Kumar wrote:
> -added assert-deassert PERST implementation
> for physical ports (both USP and DSP's).
> -assert PERST involves bg operation for holding 100ms.
> -reset PPB implementation for physical ports.
>
> Signed-off-by: Arpit Kumar
Hi Arpit,
Mino
On Thu, 10 Jul 2025 20:13:37 +0530
Arpit Kumar wrote:
> -Storing physical ports info during enumeration.
> -Refactored changes using physical ports info for
> Identify Switch Device (Opcode 5100h) & Get Physical Port State
> (Opcode 5101h) physical switch FM-API command set.
>
> Signed-off-by:
On Fri, 18 Jul 2025 21:35:45 +0800
peng guo wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> 9p device fails to initialize properly. The kernel reports the following:
>
> virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1
> 9p
On Mon, 21 Jul 2025 18:22:28 +0100
wrote:
> From: Shiju Jose
>
> Memory sparing is defined as a repair function that replaces a portion of
> memory with a portion of functional memory at that same DPA. The
> subclasses for this operation vary in terms of the scope of the sparing
> being perform
On Mon, 21 Jul 2025 18:22:27 +0100
wrote:
> From: Davidlohr Bueso
I tweaked the title to mention Post Package Repair. If anyone is ever
looking for that particular maintenance command they might want to know
it is in here from the title.
>
> This adds initial support for the Maintenance comm
On Mon, 21 Jul 2025 18:22:22 +0100
wrote:
> From: Shiju Jose
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in
On Thu, 24 Jul 2025 03:43:56 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Jul 18, 2025 at 09:35:45PM +0800, peng guo wrote:
> > When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> > 9p device fails to initialize properly. The kernel reports the following:
> >
> > vi
On Fri, 18 Jul 2025 19:20:45 +0300
Vadim Chichikalyuk wrote:
> Previous patch changed the SPCR ACPI table for AArch64 virt:
> @@ -15,2 +15,2 @@
> -[008h 0008 001h]Revision : 02
> -[009h 0009 001h]Checksum : B1
> +[008h 0008 001h]Revision
On Fri, 18 Jul 2025 19:20:42 +0300
Vadim Chichikalyuk wrote:
> The UART clock frequency field of the SPCR table was added in revision 3.
> Currently, build_spcr() treats revision 3 tables the same as revision 2 and
> only includes this field in revision 4 tables.
Given this isn't in the ACPI spe
On Fri, 18 Jul 2025 19:20:44 +0300
Vadim Chichikalyuk wrote:
> On the ARM virt machine, there is currently no way to programmatically
> discover the frequency of the UART reference clock solely through the use of
> UEFI/ACPI (without the DTB). The SPCR table can include this information
> as of r
On Fri, 18 Jul 2025 19:20:43 +0300
Vadim Chichikalyuk wrote:
> Signed-off-by: Vadim Chichikalyuk
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-di
On Tue, 15 Jul 2025 10:01:21 -0700
Nicolin Chen wrote:
> On Tue, Jul 15, 2025 at 11:29:41AM +0100, Jonathan Cameron wrote:
> > > +if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,
> > > + IOMMU_VIOMMU_TYPE_ARM_SMMUV3,
> > > +
On Mon, 14 Jul 2025 16:59:41 +0100
Shameer Kolothum wrote:
> Now user can set "accel=on". Have fun!
>
> Signed-off-by: Shameer Kolothum
Hard to argue with this one ;)
Reviewed-by: Jonathan Cameron
> ---
> hw/arm/smmu-common.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm
On Mon, 14 Jul 2025 16:59:40 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SIDSIZE
On Mon, 14 Jul 2025 16:59:39 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Use the provided smmuv3-accel helper functions to issue the
> invalidation commands to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-internal.h | 11 +++
On Mon, 14 Jul 2025 16:59:38 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Helpers will batch the commands and issue at once to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-accel.c| 65 +
On Mon, 14 Jul 2025 16:59:34 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -If found an existing viommu reuse that.
>(Devices behind the same physical SMMU should share an S2 HWPT)
> -Else,
> Allocate a viommu with the nested parent S2
On Mon, 14 Jul 2025 16:59:32 +0100
Shameer Kolothum wrote:
> Accelerated SMMUv3 is only useful when the device can take advantage of
> the host's SMMUv3 in nested mode. To keep things simple and correct, we
> only allow this feature for vfio-pci endpoint devices that use the iommufd
> backend. We
On Mon, 14 Jul 2025 16:59:31 +0100
Shameer Kolothum wrote:
> Also setup specific PCIIOMMUOps for accel SMMUv3 as accel
> SMMUv3 will have different handling for those ops callbacks
> in subsequent patches.
>
> The "accel" property is not yet added, so users cannot set it at this
> point. It will
On Mon, 14 Jul 2025 16:59:30 +0100
Shameer Kolothum wrote:
> Allows to retrieve the PCIIOMMUOps based on the SMMU type. This will be
> useful when we add support for accelerated SMMUV3 in subsequent patches
> as that requires a different set of callbacks for iommu ops.
>
> No special handling is
On Mon, 14 Jul 2025 16:59:29 +0100
Shameer Kolothum wrote:
> Subsequent patches for smmuv3 accel support will make use of this.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
Various trivial things inline. In general looks fine.
J
> ---
> hw/ar
On Mon, 14 Jul 2025 16:59:28 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate an iommufd device's virtual device (in the user
> space) per a viommu instance.
Same trivial suggestion as in patch 1. Also feel free to ignore.
On Mon, 14 Jul 2025 16:59:27 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate a viommu object.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
One trivial comment inline. Feel free to ignore.
> ---
> backends/iomm
On Mon, 14 Jul 2025 10:04:44 +0200
Eric Auger wrote:
> This series enables ACPI PCI hotplug/hotunplug on ARM.
> It is not enabled by default and ACPI PCI hotplug can
> be selected by setting:
>
> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>
> Expected benefits should be similar t
From: Anisa Su
Prepatory patch for following FMAPI Add/Release Patches. Refactors part
of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
function to create DC Event Records and insert in the event log.
Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
accessed b
From: Anisa Su
Add a lock on the bitmap of each CXLDCRegion in preparation for the next
patch which implements FMAPI Set DC Region Configuration. This command
can modify the block size, which means the region's bitmap must be updated
accordingly.
The lock becomes necessary when commands that add
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 88 ++
1 file changed, 88 insertions(+)
diff --git
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 of set to merge:
- Fixed blksize check in set dc region config
- Added check that it is a power of 2 (and host-ut
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 ++
hw/cxl/cxl-mailbox-utils.c | 109
hw/mem
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