On Mon, 4 Aug 2025 22:24:21 +0800
peng guo wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU on a
> physical server, the 9p device fails to initialize properly. The kernel
> reports
> the following error:
>
> virtio: device uses modern interface but does not
On Tue, 29 Jul 2025 09:54:39 -0700
Davidlohr Bueso wrote:
> Hello,
>
> The following allows support for component basic back invalidation discovery
> and config, by exposing the BI routing table and decoder registers. Instead
> of going the type2[1] route, this series proposes adding support for
On Wed, 30 Jul 2025 17:52:45 -0300
Fabiano Rosas wrote:
> Don't use the 'max' cpu for migration testing of aarch64. That cpu
> does not provide a stable set of features and is expected to break
> migration from time to time.
Whilst I can see the motivation, doesn't this leave us with a lack of
c
On Wed, 30 Jul 2025 15:21:41 +0300
Manos Pitsidianakis wrote:
> NVDIMM is used for fast rootfs with EROFS, for example by kata
> containers. To allow booting with static NVDIMM memory, add them to the
> device tree in arm virt machine.
>
> This allows users to boot directly with nvdimm memory de
On Sat, 26 Jul 2025 20:50:35 +0800
peng guo wrote:
> On Fri, Jul 25, 2025 at 02:53:37PM +0100, Jonathan Cameron wrote:
> > On Fri, 18 Jul 2025 21:35:45 +0800
> > peng guo wrote:
> >
> > > When using a CXL Type 3 device together with a virtio 9p device in QE
On Tue, 17 Jun 2025 12:06:49 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> Define a new CXL host bridge type (TYPE_CXL_HOST). This is an
> independent CXL host bridge which combined GPEX features (ECAM, MMIO
> windows and irq) and CXL Host Bridge Component Registers (CHBCR).
>
> The root bus
On Tue, 17 Jun 2025 12:06:48 +0800
wangyuquan wrote:
> This renames some descriptions and definitions of pxb cxl host
> bridge, since the original names can be confusing.
>
> Signed-off-by: Yuquan Wang
Fair enough.
Reviewed-by: Jonathan Cameron
> ---
> hw/pci-bridge/pci
On Tue, 17 Jun 2025 12:19:46 +0800
wangyuquan wrote:
> From: Yuquan Wang
>
> This creates a specific CXL host bridge (0001:00) with two cxl
> root ports on sbsa-ref. And the memory layout provides separate
> space windows for the cxl host bridge in the sbsa-ref memmap:
>
> - 64K CXL Host Brid
On Thu, 10 Jul 2025 20:13:38 +0530
Arpit Kumar wrote:
> -added assert-deassert PERST implementation
> for physical ports (both USP and DSP's).
> -assert PERST involves bg operation for holding 100ms.
> -reset PPB implementation for physical ports.
>
> Signed-off-by: Arpit Kumar
Hi Arpit,
Mino
On Thu, 10 Jul 2025 20:13:37 +0530
Arpit Kumar wrote:
> -Storing physical ports info during enumeration.
> -Refactored changes using physical ports info for
> Identify Switch Device (Opcode 5100h) & Get Physical Port State
> (Opcode 5101h) physical switch FM-API command set.
>
> Signed-off-by:
On Fri, 18 Jul 2025 21:35:45 +0800
peng guo wrote:
> When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> 9p device fails to initialize properly. The kernel reports the following:
>
> virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1
> 9p
' flag set in the CXL DRAM error record.
>
> CXL spec 3.2 section 8.2.10.7.2.3 describes the memory sparing feature
> discovery and configuration.
>
> CXL spec 3.2 section 8.2.10.7.1.4 describes the device's memory sparing
> maintenance operation feature.
>
> Add em
; configuration.
>
> CXL spec 3.2 section 8.2.10.7.2.2 describes the hPPR feature discovery and
> configuration.
>
> CXL spec 3.2 section 8.2.10.2.1.4 Table 8-60 describes the Memory Sparing
> Event Record.
>
> Signed-off-by: Davidlohr Bueso
> Co-developed-by: Shiju
e optional parameters in the related
> CXL events reporting and in the QMP commands to inject CXL events.
>
> Signed-off-by: Jonathan Cameron
I'll fix up, but this shouldn't have my SoB on the thread.
I'll add that when applying to my staging tree and for sending
this as part
On Thu, 24 Jul 2025 03:43:56 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Jul 18, 2025 at 09:35:45PM +0800, peng guo wrote:
> > When using a CXL Type 3 device together with a virtio 9p device in QEMU, the
> > 9p device fails to initialize properly. The kernel reports the following:
> >
> > vi
On Fri, 18 Jul 2025 19:20:45 +0300
Vadim Chichikalyuk wrote:
> Previous patch changed the SPCR ACPI table for AArch64 virt:
> @@ -15,2 +15,2 @@
> -[008h 0008 001h]Revision : 02
> -[009h 0009 001h]Checksum : B1
> +[008h 0008 001h]Revision
yuk
Code looks fine so with those additions to the description
Reviewed-by: Jonathan Cameron
> ---
> hw/acpi/aml-build.c | 20 +++-
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 1e685f982f..9
n
> as of revision 3.
>
> Bump the revision to 3 and add the clock frequency of 24 MHz to the table.
Maybe add something on why you aren't just skipping forwards to 4 and filling
in the rest of the stuff?
>
> Signed-off-by: Vadim Chichikalyuk
Reviewed-by: Jonathan Camero
On Fri, 18 Jul 2025 19:20:43 +0300
Vadim Chichikalyuk wrote:
> Signed-off-by: Vadim Chichikalyuk
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-di
On Tue, 15 Jul 2025 10:01:21 -0700
Nicolin Chen wrote:
> On Tue, Jul 15, 2025 at 11:29:41AM +0100, Jonathan Cameron wrote:
> > > +if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,
> > > + I
On Mon, 14 Jul 2025 16:59:41 +0100
Shameer Kolothum wrote:
> Now user can set "accel=on". Have fun!
>
> Signed-off-by: Shameer Kolothum
Hard to argue with this one ;)
Reviewed-by: Jonathan Cameron
> ---
> hw/arm/smmu-common.c | 1 +
> 1 file changed, 1 inser
On Mon, 14 Jul 2025 16:59:40 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SIDSIZE
On Mon, 14 Jul 2025 16:59:39 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Use the provided smmuv3-accel helper functions to issue the
> invalidation commands to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-internal.h | 11 +++
On Mon, 14 Jul 2025 16:59:38 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Helpers will batch the commands and issue at once to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-accel.c| 65 +
On Mon, 14 Jul 2025 16:59:34 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -If found an existing viommu reuse that.
>(Devices behind the same physical SMMU should share an S2 HWPT)
> -Else,
> Allocate a viommu with the nested parent S2
On Mon, 14 Jul 2025 16:59:32 +0100
Shameer Kolothum wrote:
> Accelerated SMMUv3 is only useful when the device can take advantage of
> the host's SMMUv3 in nested mode. To keep things simple and correct, we
> only allow this feature for vfio-pci endpoint devices that use the iommufd
> backend. We
On Mon, 14 Jul 2025 16:59:31 +0100
Shameer Kolothum wrote:
> Also setup specific PCIIOMMUOps for accel SMMUv3 as accel
> SMMUv3 will have different handling for those ops callbacks
> in subsequent patches.
>
> The "accel" property is not yet added, so users cannot set it at this
> point. It will
On Mon, 14 Jul 2025 16:59:30 +0100
Shameer Kolothum wrote:
> Allows to retrieve the PCIIOMMUOps based on the SMMU type. This will be
> useful when we add support for accelerated SMMUV3 in subsequent patches
> as that requires a different set of callbacks for iommu ops.
>
> No special handling is
On Mon, 14 Jul 2025 16:59:29 +0100
Shameer Kolothum wrote:
> Subsequent patches for smmuv3 accel support will make use of this.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
Various trivial things inline. In general looks fine.
J
> ---
> hw/ar
On Mon, 14 Jul 2025 16:59:28 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate an iommufd device's virtual device (in the user
> space) per a viommu instance.
Same trivial suggestion as in patch 1. Also feel free to ignore.
On Mon, 14 Jul 2025 16:59:27 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate a viommu object.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
One trivial comment inline. Feel free to ignore.
> ---
> backends/iomm
On Mon, 14 Jul 2025 10:04:44 +0200
Eric Auger wrote:
> This series enables ACPI PCI hotplug/hotunplug on ARM.
> It is not enabled by default and ACPI PCI hotplug can
> be selected by setting:
>
> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>
> Expected benefits should be similar t
by cxl-mailbox-utils.c and cxl-events.c, where the helper
function is defined.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 of set to merge: Picked up Fan's tag. Thanks!
---
include/hw/cxl/cxl.h| 1 +
include/hw/cxl/cxl_device.h | 4
h
that add/release extents
(meaning they update the bitmap too) are enabled on a different CCI than
the CCI on which the FMAPI commands are enabled.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/mem/cxl_type3.c | 4 ++
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 88 ++
1 file changed, 88 insertions(+)
diff
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 of set to merge:
- Fixed blksize check in set dc region config
- Added check that it is a power of 2 (and host
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 ++
hw/cxl/cxl-mailbox-utils.c | 109
hw
From: Anisa Su
FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4
Very similar to previously implemented command 0x4801.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 for merge:
- Added a missing : in a comment similar to Fan
From: Anisa Su
FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 106 +
1 file changed, 106 insertions(+)
diff
From: Anisa Su
Move definition/enum to cxl_events.h for shared use in next patch
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_events.h | 15 +++
hw/mem/cxl_type3.c | 15 ---
2 files changed, 15 insertions
From: Anisa Su
Add booleans to DC Region struct to represent dsmas flags (defined in CDAT) in
preparation for the next command, which returns the flags in the next mailbox
command 0x5601.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 for merge
- Added
From: Anisa Su
FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section 7.6.7.6.1.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 series for merge.
- Modify the code that fills in the support blk sizes to not
do effectively 2**log2(x) when
ot;total_extent_count" to include
both accepted and pending extents counting.
Signed-off-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 3 ++-
hw/cxl/cxl-mailbox-utils.c | 26 ++
hw/mem/cxl_type3.c | 1 +
3 files changed,
v2:
- Missing colon and tags (Fan)
- Simpler handling block size parameters. The spec constrains these to
be power of 2 so the v1 code of BITUL((int)log2(x) is equivalent of
just using x directly. (Michael)
- Check for power of 2 (Fan + Anisa)
Hi Michael,
I consider these ready for upstream
On Mon, 14 Jul 2025 17:21:10 +
Anisa Su wrote:
> On Mon, Jul 14, 2025 at 06:02:26PM +0100, Jonathan Cameron wrote:
> > On Mon, 14 Jul 2025 09:45:31 -0700
> > Fan Ni wrote:
> >
> > > On Mon, Jul 14, 2025 at 03:16:38PM +0100, Jonathan Cameron wrote:
> &
On Mon, 14 Jul 2025 09:45:31 -0700
Fan Ni wrote:
> On Mon, Jul 14, 2025 at 03:16:38PM +0100, Jonathan Cameron wrote:
> > On Mon, 14 Jul 2025 15:15:12 +0100
> > Jonathan Cameron wrote:
> >
> > > On Mon, 14 Jul 2025 15:02:18 +0100
> > > Jonathan Cameron
ard for the OS to know the whole system is homogeneous or not
> > > > (actually we're in the current implementation) since no parent node
> > > > to telling the identical implementation informentation. Add a
> > > > root node for indicating this.
> > &g
On Mon, 14 Jul 2025 15:02:18 +0100
Jonathan Cameron wrote:
> On Mon, 14 Jul 2025 05:32:19 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Jul 02, 2025 at 05:02:13PM +0100, Jonathan Cameron wrote:
> > > From: Anisa Su
> > >
> > > FM DC
On Mon, 14 Jul 2025 15:15:12 +0100
Jonathan Cameron wrote:
> On Mon, 14 Jul 2025 15:02:18 +0100
> Jonathan Cameron wrote:
>
> > On Mon, 14 Jul 2025 05:32:19 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Wed, Jul 02, 2025 at 05:02:13PM +
On Mon, 14 Jul 2025 05:32:19 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Jul 02, 2025 at 05:02:13PM +0100, Jonathan Cameron wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.3
> >
On Thu, 3 Jul 2025 16:23:57 +
Fan Ni wrote:
> On Wed, Jul 02, 2025 at 05:02:16PM +0100, Jonathan Cameron wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.5
> >
> > Signed-off-by
}
> Local0 [Zero] = BSEL /* \_SB_.PCI0.BSEL */
> Local0 [One] = ASUN /* \_SB_.PCI0.S08_.ASUN */
> Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
> }
>
> Name (_SUN, One) // _SUN: Slot User
On Thu, 3 Jul 2025 14:35:35 +0200
Eric Auger wrote:
> The disassembled DSDT table is given below
I'd suggest maybe a spot of cropping to bring this down to a reasonable length.
See inline.
Otherwise LGTM
Reviewed-by: Jonathan Cameron
>
> * Original Table Header:
>
On Thu, 3 Jul 2025 14:35:32 +0200
Eric Auger wrote:
> Set up the IO registers used to communicate between QEMU
> and ACPI.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
gt; The GED device uses a dedicated MMIO region that will be mapped
> by the machine code.
>
> At this point the GED still does not support PCI device hotplug in
> its TYPE_HOTPLUG_HANDLER implementation. This will come in a
> subsequent patch.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
; +Name (_ADR, Zero) // _ADR: Address
> +}
> +
> +Device (S08)
> +{
> +Name (_ADR, 0x0001) // _ADR: Address
> + }
> +
> +Device (S10)
> +{
> +Name (_ADR, 0x0002) // _ADR: Address
> +}
> +}
> }
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
ortant though given how short a time this lasts
for.
Reviewed-by: Jonathan Cameron
>
> Signed-off-by: Eric Auger
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 -
> tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5158 bytes
> 2 files changed, 1 deletion
On Thu, 3 Jul 2025 14:35:17 +0200
Eric Auger wrote:
> The test misses a variant and this puts the mess on subsequent
> rebuild-expected-aml.sh where a first DSDT reference blob is
> overriden by another one.
>
> Signed-off-by: Eric Auger
For completeness..
Reviewed-by: Jonathan Cameron
er than
base tests that has this problem but might be wrong.
Anyhow, this looks right
Reviewed-by: Jonathan Cameron
> ---
> tests/qtest/bios-tables-test.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
>
On Thu, 3 Jul 2025 10:16:50 +0100
wrote:
> From: Shiju Jose
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in
Add a single complex case for aarch64 virt machine.
Given existing much more comprehensive tests for x86 cover the common
functionality, a single test should be enough to verify that the aarch64
part continues to work.
Tested-by: Itaru Kitayama
Reviewed-by: Eric Auger
Signed-off-by: Jonathan
: Eric Auger
Signed-off-by: Jonathan Cameron
---
v17: Tag from Eric plus expanded on the intro text for the arm example.
---
docs/system/devices/cxl.rst | 11 +++
1 file changed, 11 insertions(+)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index e307caf3f8
: Jonathan Cameron
---
v17: Updated patch description to cover some feedback from Eric.
Added a comment in the high memory map where the CXL
Fixed Memory Windows will be placed. Given the size can only
be established at runtime, explicit entries don't work. This
is simil
n x86 only implementation.
Reviewed-by: Li Zhijian
Tested-by: Li Zhijian
Signed-off-by: Jonathan Cameron
---
v16: Add a comment about there being no dynamic state so no reset
or migration support is needed. (Peter Maydell)
---
include/hw/cxl/cxl.h | 4 +-
include/hw/cxl/cxl_host.h
-off-by: Jonathan Cameron
---
v17: Tag from Eric.
---
include/hw/cxl/cxl.h | 1 +
hw/cxl/cxl-host.c| 9 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 3ae4303383..83096b2300 100644
--- a/include/hw/cxl/cxl.h
+++ b
possible to support limited use with KVM but
that needs additional patches not yet ready for upstream. The challenge
is interleave - and the solution is don't interleave if you want to run
with KVM.
Jonathan Cameron (5):
hw/cxl-host: Add an index field to CXLFixedMemoryWindow
hw/cxl:
that we don't have a test for this case (yet) - later in this series
there is one and I guess Gustavo knew that was coming!
Anyhow, the patch looks good to me.
Reviewed-by: Jonathan Cameron
> ---
> hw/arm/virt-acpi-build.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --g
On Thu, 3 Jul 2025 04:17:28 +
Fan Ni wrote:
> On Thu, Jun 26, 2025 at 10:23:32PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.5
> >
> > Signed-off-by: Anisa Su
> > ---
>
> Minor commen
On Thu, 3 Jul 2025 04:21:25 +
Fan Ni wrote:
> On Thu, Jun 26, 2025 at 10:23:33PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.6
> >
> > Signed-off-by: Anisa Su
> > ---
> Minor comments
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/hw/cxl/cxl
by cxl-mailbox-utils.c and cxl-events.c, where the helper
function is defined.
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl.h| 1 +
include/hw/cxl/cxl_device.h | 4
hw/cxl/cxl-events.c | 38 +
hw/cxl/cxl
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 ++
hw/cxl/cxl-mailbox-utils.c | 109
hw/mem/cxl_type3.c
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 3 ++
include/hw/cxl/cxl_mailbox.h | 6 +++
hw/cxl/cxl-mailbox-utils.c | 86
From: Anisa Su
FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4
Very similar to previously implemented command 0x4801.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 76
that add/release extents
(meaning they update the bitmap too) are enabled on a different CCI than
the CCI on which the FMAPI commands are enabled.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/mem/cxl_type3.c | 4 ++
From: Anisa Su
Move definition/enum to cxl_events.h for shared use in next patch
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_events.h | 15 +++
hw/mem/cxl_type3.c | 15 ---
2 files changed, 15 insertions
From: Anisa Su
FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 106 +
1 file changed, 106 insertions(+)
diff
From: Anisa Su
FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section 7.6.7.6.1.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/cxl/cxl-mailbox-utils.c | 59 +
hw/mem
From: Anisa Su
Add booleans to DC Region struct to represent dsmas flags (defined in CDAT) in
preparation for the next command, which returns the flags in the next mailbox
command 0x5601.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl
Hi Michael,
I consider these ready for upstream. They are only lightly tweaked from
Anisa's last posting to drop some long lines and change a few patch
titles + drag them to be directly based on upstream rather than on top
of some stuff on my gitlab tree (trivial fuzz + context stuff only in
the
ot;total_extent_count" to include
both accepted and pending extents counting.
Signed-off-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 3 ++-
hw/cxl/cxl-mailbox-utils.c | 26 ++
hw/mem/cxl_type3.c | 1 +
3 files changed,
On Tue, 1 Jul 2025 18:12:39 +0200
Eric Auger wrote:
> Hi Jonathan,
> On 7/1/25 5:52 PM, Jonathan Cameron wrote:
> > On Tue, 1 Jul 2025 17:34:36 +0200
> > Eric Auger wrote:
> >
> >> Hi Jonathan,
> >>
> >> On 6/25/25 6:19 PM, Jonathan Cameron
On Tue, 1 Jul 2025 17:34:36 +0200
Eric Auger wrote:
> Hi Jonathan,
>
> On 6/25/25 6:19 PM, Jonathan Cameron via wrote:
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extende
On Tue, 1 Jul 2025 15:26:26 +0200
Eric Auger wrote:
> Hi Jonathan,
>
> On 6/25/25 6:19 PM, Jonathan Cameron via wrote:
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extende
On Fri, 27 Jun 2025 16:38:16 +
Anisa Su wrote:
> On Fri, Jun 27, 2025 at 10:48:59AM +0100, Jonathan Cameron wrote:
> > On Thu, 26 Jun 2025 23:41:15 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > Per the spe
On Thu, 26 Jun 2025 22:23:33 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
A few more long line related tweaks.
> ---
> hw/cxl/cxl-mailbox-utils.c | 79 ++
On Thu, 26 Jun 2025 22:23:32 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
There are a few long lines in here check patch doesn't like.
I tweaked as described inline whilst picking them up.
>
> Si
On Thu, 26 Jun 2025 22:23:26 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section
> 7.6.7.6.2
>
> Reviewed-by: Fan Ni
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 103
t_port_hpoff tests static-acpi index
> on a root port with disabled hotplug
>
> Signed-off-by: Gustavo Romero
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
t/DSDT.hpoffacpiindex
>
> Signed-off-by: Gustavo Romero
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 11:55:18 +0200
Eric Auger wrote:
> Set up the IO registers used to communicate between QEMU
> and ACPI.
>
> Signed-off-by: Eric Auger
Follow on comment inline. Otherwise LGTM
Reviewed-by: Jonathan Cameron
>
> ---
> v2 -> v3:
&
d it becomes difficult to guess the index of
> a region. Better refer to a region by its name.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 11:55:14 +0200
Eric Auger wrote:
> QEMU will notify the OS about PCI hotplug/hotunplug events through
> GED interrupts. Let the GED device handle a new PCI hotplug event.
> On its occurrence it calls the \\_SB.PCI0.PCNT method with the BLCK
> mutex held.
>
> The GED device us
On Fri, 27 Jun 2025 11:55:15 +0200
Eric Auger wrote:
> Add a subsection to migrate the AcpiPciHpState state.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
that change is to be consistent with the forecoming ARM
> implementation where the machine passes the root bus (steming from GPEX)
> to the GED device through a link property.
>
> Signed-off-by: Eric Auger
> Suggested-by: Igor Mammedov
Seems reasonable to me.
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 11:55:09 +0200
Eric Auger wrote:
> Modify the DSDT ACPI table to enable ACPI PCI hotplug.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 12:00:51 +0200
Eric Auger wrote:
> Hi,
>
> On 6/27/25 11:55 AM, Eric Auger wrote:
> > Changes relate to the introduction of pieces related to
> > acpi-index static support along with root ports with no hotplug.
> >
> > +
> > +Scope (\_SB.PCI0)
> > +{
> > +Meth
i386 code so LGTM
Reviewed-by: Jonathan Cameron
s slightly silly to give tags to these, but for FWIW
Reviewed-by: Jonathan Cameron
> ---
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-
On Fri, 27 Jun 2025 11:55:05 +0200
Eric Auger wrote:
> Move aml_pci_edsm to pci-bridge.c since we want to reuse that for
> ARM and acpi-index support. Also rename it into build_pci_bridge_edsm.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
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