On 2023/10/31 19:06, gaosong wrote:
在 2023/10/31 下午5:13, Jiajie Chen 写道:
On 2023/10/31 17:11, gaosong wrote:
在 2023/10/30 下午7:54, Jiajie Chen 写道:
On 2023/10/30 16:23, gaosong wrote:
在 2023/10/28 下午9:09, Jiajie Chen 写道:
On 2023/10/26 14:54, gaosong wrote:
在 2023/10/26 上午9:38, Jiajie
On 2023/10/31 17:11, gaosong wrote:
在 2023/10/30 下午7:54, Jiajie Chen 写道:
On 2023/10/30 16:23, gaosong wrote:
在 2023/10/28 下午9:09, Jiajie Chen 写道:
On 2023/10/26 14:54, gaosong wrote:
在 2023/10/26 上午9:38, Jiajie Chen 写道:
On 2023/10/26 03:04, Richard Henderson wrote:
On 10/25/23 10:13
On 2023/10/30 16:23, gaosong wrote:
在 2023/10/28 下午9:09, Jiajie Chen 写道:
On 2023/10/26 14:54, gaosong wrote:
在 2023/10/26 上午9:38, Jiajie Chen 写道:
On 2023/10/26 03:04, Richard Henderson wrote:
On 10/25/23 10:13, Jiajie Chen wrote:
On 2023/10/24 07:26, Richard Henderson wrote:
See target
On 2023/10/26 14:54, gaosong wrote:
在 2023/10/26 上午9:38, Jiajie Chen 写道:
On 2023/10/26 03:04, Richard Henderson wrote:
On 10/25/23 10:13, Jiajie Chen wrote:
On 2023/10/24 07:26, Richard Henderson wrote:
See target/arm/tcg/translate-a64.c, gen_store_exclusive,
TCGv_i128 block.
See target
On 2023/10/26 03:04, Richard Henderson wrote:
On 10/25/23 10:13, Jiajie Chen wrote:
On 2023/10/24 07:26, Richard Henderson wrote:
See target/arm/tcg/translate-a64.c, gen_store_exclusive, TCGv_i128
block.
See target/ppc/translate.c, gen_stqcx_.
The situation here is slightly different
On 2023/10/24 14:10, Jiajie Chen wrote:
On 2023/10/24 07:26, Richard Henderson wrote:
On 10/23/23 08:29, Jiajie Chen wrote:
This patch series implements the new instructions except sc.q,
because I do not know how to match a pair of ll.d to sc.q.
There are a couple of examples within the
On 2023/10/24 07:26, Richard Henderson wrote:
On 10/23/23 08:29, Jiajie Chen wrote:
This patch series implements the new instructions except sc.q,
because I do not know how to match a pair of ll.d to sc.q.
There are a couple of examples within the tree.
See target/arm/tcg/translate-a64.c
On 2023/10/23 23:49, David Hildenbrand wrote:
Why?
On 23.10.23 17:29, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
include/exec/memop.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index a86dc6743a..834327c62d 100644
--- a/include
On 2023/10/23 23:29, Jiajie Chen wrote:
The new instructions are introduced in LoongArch v1.1:
- amcas.b
- amcas.h
- amcas.w
- amcas.d
- amcas_db.b
- amcas_db.h
- amcas_db.w
- amcas_db.d
The new instructions are gated by CPUCFG2.LAMCAS.
Signed-off-by: Jiajie Chen
---
target/loongarch
improve performance by reducing precision, we use the
existing softfloat implementation.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 1 +
target/loongarch/disas.c | 12
target/loongarch/insn_trans/trans_farith.c.inc | 4
The new instructions are introduced in LoongArch v1.1:
- amcas.b
- amcas.h
- amcas.w
- amcas.d
- amcas_db.b
- amcas_db.h
- amcas_db.w
- amcas_db.d
The new instructions are gated by CPUCFG2.LAMCAS.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h| 1 +
target
cessor.
This patch series implements the new instructions except sc.q, because I
do not know how to match a pair of ll.d to sc.q.
Jiajie Chen (5):
include/exec/memop.h: Add MO_TESB
target/loongarch: Add am{swap/add}[_db].{b/h}
target/loongarch: Add amcas[_db].{b/h/w/d}
target/loongarc
Signed-off-by: Jiajie Chen
---
include/exec/memop.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index a86dc6743a..834327c62d 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -140,6 +140,7 @@ typedef enum MemOp {
MO_TEUL
The new instructions are introduced in LoongArch v1.1:
- amswap.b
- amswap.h
- amadd.b
- amadd.h
- amswap_db.b
- amswap_db.h
- amadd_db.b
- amadd_db.h
The instructions are gated by CPUCFG2.LAM_BH.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 1 +
target
Add the following instructions in LoongArch v1.1:
- llacq.w
- screl.w
- llacq.d
- screl.d
They are guarded by CPUCFG2.LLACQ_SCREL.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h| 1 +
target/loongarch/disas.c | 4
.../loongarch
Since support for LSX and LASX is landed in QEMU recently, we can update
HWCAPS accordingly.
Signed-off-by: Jiajie Chen
---
linux-user/elfload.c | 8
1 file changed, 8 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index db75cd4b33..f11f25309e 100644
--- a
(use_lsx_instructions) {
+if (cpuinfo & CPUINFO_LSX) {
tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
Reviewed-by: Jiajie Chen
d_a64_i128:
-return C_O2_I1(r, r, r);
+return C_N2_I1(r, r, r);
case INDEX_op_qemu_st_a32_i128:
case INDEX_op_qemu_st_a64_i128:
Reviewed-by: Jiajie Chen
.add(files('cpuinfo-i386.c'))
+elif cpu == 'loongarch64'
+ util_ss.add(files('cpuinfo-loongarch.c'))
elif cpu in ['ppc', 'ppc64']
util_ss.add(files('cpuinfo-ppc.c'))
endif
Reviewed-by: Jiajie Chen
1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
Reviewed-by: Jiajie Chen
HW_FLAGS_EUEN_ASXE acccidentally conflicts with HW_FLAGS_CRMD_PG,
enabling LASX instructions even when CSR_EUEN.ASXE=0.
Closes: https://gitlab.com/qemu-project/qemu/-/issues/1907
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg
Pass vece to tcg_target_const_match() to allow correct interpretation of
const args of vector ops.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc| 2 +-
tcg
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65
3 files changed, 67 insertions(+)
diff --git a/tcg/loongarch64/tcg
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 44
tcg/loongarch64
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 24
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg
_vec/st_vec/ld_vec/cmp_vec/add_vec/sub_vec generation
- Lower not_vec/shi_vec/roti_vec/rotv_vec
Jiajie Chen (16):
tcg/loongarch64: Import LSX instructions
tcg/loongarch64: Lower basic tcg vec ops to LSX
tcg: pass vece to tcg_target_const_match()
tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 14 ++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg
If LSX is available, use LSX instructions to implement 128-bit load &
store when MO_128 is required, otherwise use two 64-bit loads & stores.
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target.c.inc | 59 +
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 61
3 files changed, 63 insertions(+)
diff --git a/tcg
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
On 2023/9/3 09:06, Richard Henderson wrote:
On 9/1/23 22:02, Jiajie Chen wrote:
If LSX is available, use LSX instructions to implement 128-bit load &
store.
Is this really guaranteed to be an atomic 128-bit operation?
Song Gao, please check this.
Or, as for many vector processors
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
3 files changed, 62 insertions(+)
diff --git a/tcg
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 14 ++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 44
tcg/loongarch64
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg
If LSX is available, use LSX instructions to implement 128-bit load &
store.
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 42
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 24
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65
3 files changed, 67 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
/add_vec/sub_vec for better const arg
handling
- Implement 128-bit load & store using vldx/vstx
Changes since v1:
- Optimize dupi_vec/st_vec/ld_vec/cmp_vec/add_vec/sub_vec generation
- Lower not_vec/shi_vec/roti_vec/rotv_vec
Jiajie Chen (16):
tcg/loongarch64: Import LSX instructions
Pass vece to tcg_target_const_match() to allow correct interpretation of
const args of vector ops.
Signed-off-by: Jiajie Chen
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc| 2 +-
tcg/loongarch64/tcg-target.c.inc | 2
On 2023/9/2 01:48, Richard Henderson wrote:
On 9/1/23 10:28, Jiajie Chen wrote:
On 2023/9/2 01:24, Richard Henderson wrote:
On 9/1/23 02:30, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
On 2023/9/2 01:24, Richard Henderson wrote:
On 9/1/23 02:30, Jiajie Chen wrote:
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
2 files changed, 61 insertions(+)
Reviewed-by: Richard
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 44
tcg/loongarch64/tcg-target.h | 8 ++---
3
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 58
2 files changed, 59 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 24
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg
Jiajie Chen (14):
tcg/loongarch64: Import LSX instructions
tcg/loongarch64: Lower basic tcg vec ops to LSX
tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
tcg/loongarch64: Lower add/sub_vec to vadd/vsub
tcg/loongarch64: Lower vector bitwise operations
tcg/loongarch64: Lower neg_vec to
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 14 ++
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 6fe319a77e..c4e9e0309e
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 21 +
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 60
2 files changed, 61 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 37b3f80bf9
There seems to some problem with the email server, try my another email
address to send this email.
On 2023/8/29 00:57, Richard Henderson wrote:
On 8/28/23 08:19, Jiajie Chen wrote:
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned
vece
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 35
tcg/loongarch64/tcg-target.h | 6 +++---
2 files changed, 38 insertions(+), 3 deletions(-)
diff
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/tcg
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 10 ++
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 24
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 32
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 25 +
2 files changed, 26 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 37b3f80bf9
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 8
tcg/loongarch64/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 819dcdba77..bca24b6a20 100644
--- a/tcg
This patch series allows qemu to utilize LSX instructions on LoongArch
machines to execute TCG vector ops.
Jiajie Chen (11):
tcg/loongarch64: Import LSX instructions
tcg/loongarch64: Lower basic tcg vec ops to LSX
tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
tcg/loongarch64: Lower add
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
---
tcg/loongarch64/tcg-target.c.inc | 16
1 file changed, 16 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index cc80e5fa20..eb340a6493 100644
--- a/tcg
adhere to the same logical id
mapping.
Can pptt table parse error be fixed if cpu dsdt table is added?
Regards
Bibo Mao
在 2023/8/20 18:56, Jiajie Chen 写道:
In hw/acpi/aml-build.c:build_pptt() function, the code assumes that the
ACPI processor id equals to the cpu index, for example if we have
;-smp
8,sockets=1,cores=4,threads=2" is passed:
Thread(s) per core: 2
Core(s) per socket: 2
Socket(s): 2
The detection of number of sockets is still wrong, but that is out of
scope of the commit.
Signed-off-by: Jiajie Chen
---
hw/loongarch/acpi-build.c | 2 +-
1 file changed, 1
On 2023/8/10 15:42, xianglai li wrote:
1.Add edk2-platform submodule
2.Added loongarch UEFI BIOS support to compiled scripts.
3.The cross-compilation toolchain on x86 can be obtained from the link below:
https://github.com/loongson/build-tools/tree/2022.09.06
Cc: Paolo Bonzini
Cc: "Marc-André L
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
---
target/loongarch/cpu.c| 16
target/loongarch/cpu.h
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen
---
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
target/loongarch/translate.c | 8
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h| 9 +
target/loongarch/tlb_helper.c | 17 -
2 files changed, 17 insertions(+), 9
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the
translator to reject doubleword instructions in LA32 mode for example.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.h | 13 +
target/loongarch/translate.c | 3
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Due to lack of public documentation of la132, it is currently a
synthetic loongarch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie Chen
---
hw/loongarch/virt.c| 5
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h| 6 --
target/loongarch/tlb_helper.c | 23 ++-
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h| 7 +++
target/loongarch/tlb_helper.c | 26 +++---
2 files changed, 26 insertions(+), 7 deletions
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml| 45 +
target/loongarch/cpu.c | 10 +-
target
Add object class for future loongarch32 cpus. It is derived from the
loongarch64 object class.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.c | 19 +++
target/loongarch/cpu.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch
LoongArch64-only instructions are marked with regard to the instruction
manual Table 2. LSX instructions are not marked for now for lack of
public manual.
Signed-off-by: Jiajie Chen
---
target/loongarch/insn_trans/trans_arith.c.inc | 30
.../loongarch/insn_trans/trans_atomic.c.inc
create a separate qemu-system-loongarch32 executable, but
allow user to run loongarch32 emulation using qemu-system-loongarch64
- Add loongarch32 cpu support for virt machine
Full changes:
Jiajie Chen (11):
target/loongarch: Add function to check current arch
target/loongarch: Add new object
Add is_la64 function to check if the current cpucfg[1].arch equals to
2(LA64).
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/loongarch/cpu.h b/target
On 2023/8/9 03:26, Richard Henderson wrote:
On 8/7/23 18:54, Jiajie Chen wrote:
+static void loongarch_la464_initfn(Object *obj)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ CPULoongArchState *env = &cpu->env;
+
+ loongarch_cpu_initfn_common(env);
+
+ cpu->dtb_
On 2023/8/9 01:01, Richard Henderson wrote:
On 8/7/23 18:54, Jiajie Chen wrote:
Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or
2(LA64).
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch
On 2023/8/8 17:55, Jiajie Chen wrote:
On 2023/8/8 14:10, bibo mao wrote:
I am not familiar with gdb, is there abi breakage?
I do not know how gdb client works with gdb server with different
versions.
There seemed no versioning in the process, but rather in-code xml
validation. In gdb, the
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