The PL031 allows you to read RTCLR, which is meant to give you the last
value written. PL031State has an lr field which is used when reading
from RTCLR, and is present in the VM migration state, but we never
actually update it, so it always reads as its initial 0 value.
Signed-off-by: Jessica
ize to use
when 0 is passed in. Arguably a size of 0 shouldn't dirty at all, since
if you want to actually write then you should pass in a real size, but I
have conservatively kept the implementation as dirtying the first byte
in that case so as to avoid breaking any assumptions about that
behavi
On 8 Aug 2022, at 22:06, Conor Dooley wrote:
>
> From: Conor Dooley
>
> The subnodes of the syscon have been added to the incorrect paths.
> Rather than add them as subnodes, they were originally added to "/foo"
> and a later patch moved them to "/soc/foo". Both are incorrect & they
> should ha
l
in place of the entry point.
The uImage code is left as-is in using the U-Boot header's entry point,
since the calling convention for that entry point is the same as the SBI
one and it mirrors what U-Boot will do.
Signed-off-by: Jessica Clarke
---
hw/riscv/boot.c | 13 ++---
1 f
On 15 Oct 2021, at 01:12, Richard Henderson
wrote:
>
> On 10/14/21 4:30 PM, Michael Roth wrote:
>> Quoting Jessica Clarke (2021-08-05 14:25:45)
>>> This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
>>>
>>> This commit was misguid
On 6 Aug 2021, at 14:54, Bin Meng wrote:
> On Fri, Aug 6, 2021 at 8:58 PM Jessica Clarke wrote:
>>
>>> On Fri, Aug 6, 2021 at 10:39 AM Bin Meng wrote:
>>>>
>>>> On Fri, Aug 6, 2021 at 1:57 AM Ruinland Chuan-Tzu Tsai
>>>> wrote:
>>
On 6 Aug 2021, at 14:06, Jessica Clarke wrote:
>
>> From: Ruinalnd ChuanTzu Tsai
>>
>> In this patch we enabled custom CSR logic for Andes AX25 and A25 logic.
>> Hence csr_andes.inc.c and andes_cpu_bits.h is added.
>>
>> Signed-off-by: Dylan Jhong
> From: Ruinalnd ChuanTzu Tsai
>
> In this patch we enabled custom CSR logic for Andes AX25 and A25 logic.
> Hence csr_andes.inc.c and andes_cpu_bits.h is added.
>
> Signed-off-by: Dylan Jhong
> ---
> target/riscv/andes_cpu_bits.h | 124 +
> target/riscv/cpu.c
> On Fri, Aug 6, 2021 at 10:39 AM Bin Meng wrote:
> >
> > On Fri, Aug 6, 2021 at 1:57 AM Ruinland Chuan-Tzu Tsai
> > wrote:
> > >
> > > From: Ruinland ChuanTzu Tsai
> > >
> > > Adding option `riscv_custom` to configure script, meson.build and
> > > meson_options.txt so as to toggle custom CSR an
reflect what they're actually needed for.
Fixes: bbd2d5a8120771ec59b86a80a1f51884e0a26e53
Cc: Christian Ehrhardt
Cc: Paolo Bonzini
Cc: qemu-sta...@nongnu.org
Signed-off-by: Jessica Clarke
---
Changes in v2:
* Actually include the comment change; didn't add the hunk when
reflect what they're actually needed for.
Fixes: bbd2d5a8120771ec59b86a80a1f51884e0a26e53
Cc: Christian Ehrhardt
Cc: Paolo Bonzini
Cc: qemu-sta...@nongnu.org
Signed-off-by: Jessica Clarke
---
configure | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configure b/configure
index 9a79a
Signed-off-by: Jessica Clarke
---
Changes in v2:
* Added error to commit message
migration/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/migration/meson.build b/migration/meson.build
index 9645f44005..6fa2f8745d 100644
--- a/migration/meson.build
+++ b/migrat
Commit 3eacf70bb5a83e4775ad8003cbca63a40f70c8c2 neglected to fix this
for softmmu configs, which pull in migration's use of gnutls.
Signed-off-by: Jessica Clarke
---
migration/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/migration/meson.build b/migr
Public bug reported:
Whilst creating a flash device is recommended, -bios is extremely
useful in many cases as it automatically searches $PREFIX/share/qemu
rather than requiring the caller (be it a human or a script) to work out
where that directory is for the QEMU being called and prepend it to
These are meant to correspond to the error code reported for #PF, so fix
the definition for Instruction Fetch faults and add one for Reserved Bit
faults (checking for that is currently a TODO in x86_mmu.c).
Signed-off-by: Jessica Clarke
---
target/i386/hvf/x86_mmu.h | 3 ++-
1 file changed, 2
Buglink: https://bugs.launchpad.net/qemu/+bug/1894836
Signed-off-by: Jessica Clarke
---
target/i386/hvf/x86_cpuid.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c
index 16762b6eb4..fc1f87ec57 100644
--- a/target/i386/hvf
The Requested Privilege Level field is 2 bits, the Table Indicator field
is 1 bit and the Index field is the remaining 15 bits, with TI=0 meaning
GDT and TI=1 meaning LDT.
Signed-off-by: Jessica Clarke
---
target/i386/hvf/x86.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
0f 01 f9 is RDTSCP; use -cpu host,-rdtscp to mask out the feature. KVM
couldn't pass the feature through for a while, and HVF currently can't,
though HVF should be modified to automatically hide the feature until it
can emulate it.
--
You received this bug notification because you are a member of
On 18 Jul 2020, at 08:42, Philippe Mathieu-Daudé wrote:
> On 7/18/20 2:49 AM, Jessica Clarke wrote:
>> The specification says:
>>
>> 0x00 TIME_LOW R: Get current time, then return low-order 32-bits.
>> 0x04 TIME_HIGH R: Return high 32-bits
read.
Signed-off-by: Jessica Clarke
---
Changes since v1:
* Add time_high to goldfish_rtc_vmstate and increment version.
hw/rtc/goldfish_rtc.c | 17 ++---
include/hw/rtc/goldfish_rtc.h | 1 +
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/hw/rtc
read.
Signed-off-by: Jessica Clarke
---
hw/rtc/goldfish_rtc.c | 14 --
include/hw/rtc/goldfish_rtc.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
index 01e9d2b083..9b577bf159 100644
--- a/hw/rtc
On 26 Jun 2020, at 22:43, Alistair Francis wrote:
>
> From: Jessica Clarke
>
> Claiming an interrupt and changing the source priority both potentially
> affect whether an interrupt is pending, thus we must re-compute xEIP.
> Note that we don't put the si
(and no other actions occur
that result in a call to sifive_plic_update), but also more importantly
lost interrupts if a disabled interrupt is pending and then becomes
enabled.
Signed-off-by: Jessica Clarke
---
hw/riscv/sifive_plic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.
Signed-off-by: Jessica Clarke
---
Changes since v1
The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.
Signed-off-by: Jessica Clarke
---
hw/riscv
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