These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v9:
- Fix build errors.
v8:
- Delete RFC label.
v7:
- Fix build errors, add Reviewed-by, Acked-by.
---
Ivan Klokov (2):
target
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
Reviewed-by: Fabiano Rosas
Reviewed-by: Daniel Henrique Barboza
---
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-csr-test.c | 56
2 files changed, 57
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
Acked-by: Fabiano Rosas
Reviewed-by: Daniel
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
Reviewed-by: Fabiano Rosas
Reviewed-by: Daniel Henrique Barboza
---
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-csr-test.c | 56
2 files changed, 57
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
Acked-by: Fabiano Rosas
Reviewed-by: Daniel
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v8:
- Delete RFC label.
v7:
- Fix build errors, add Reviewed-by, Acked-by.
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v7:
- Fix build errors, add Reviewed-by, Acked-by.
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
Acked-by: Fabiano Rosas
---
hw/riscv
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
Reviewed-by: Fabiano Rosas
---
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-csr-test.c | 56
2 files changed, 57 insertions(+), 1 deletion(-)
create mode
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v6:
- Refactor code and fix checkpatch errors.
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest: QTest
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
hw/riscv/riscv_hart.c | 55
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-csr-test.c | 56
2 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/riscv-csr
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-csr-test.c | 56
2 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/riscv-csr
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v5:
- Move code from target/riscv to hw/riscv
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest: QTest
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
hw/riscv/riscv_hart.c | 65
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 +
tests/qtest/riscv-csr-test.c | 86
2 files changed, 88 insertions(+)
create mode 100644 tests/qtest/riscv-csr-test.c
diff --git
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v4:
- Change wrapper to direct call
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest: QTest example for
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu.c | 17
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu.c | 14
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v3:
- Refactor, delete additions to libqos framework
---
Ivan Klokov (2):
target/riscv: Add RISC-V CSR qtest support
tests/qtest
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 +
tests/qtest/riscv-csr-test.c | 85
2 files changed, 87 insertions(+)
create mode 100644 tests/qtest/riscv-csr-test.c
diff --git
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
---
v2:
- Refactor unit test, add missed files
---
Ivan Klokov (2):
Add RISC-V CSR qtest support
QTest example for RISC-V CSR register
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 ++
tests/qtest/riscv-csr-test.c | 47
2 files changed, 49 insertions(+)
create mode 100644 tests/qtest/riscv-csr-test.c
diff --git
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu.c | 13
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu.c | 13
Added demo for reading CSR register from qtest environment.
Signed-off-by: Ivan Klokov
---
tests/qtest/meson.build | 2 ++
tests/qtest/riscv-csr-test.c | 68
2 files changed, 70 insertions(+)
create mode 100644 tests/qtest/riscv-csr-test.c
diff --git
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.
Ivan Klokov (2):
Add RISC-V CSR qtest support
QTest example for RISC-V CSR register
target/riscv/cpu.c | 13 +++
target
read this register or not.
Fixes: ac66f2f0 ("target/riscv: pmp: Ignore writes when RW=01")
Signed-off-by: Ivan Klokov
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 162e88a90a..c0b814699e 100644
--
llegal instruction exception. This patch simultaneously
updates flag and env->vstart and to avoid inconsistency.
Signed-off-by: Ivan Klokov
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc| 88 +++---
target/riscv/i
The Sv32 page-based virtual-memory scheme described in RISCV privileged
spec Section 5.3 supports 34-bit physical addresses for RV32, so the
PMP scheme must support addresses wider than XLEN for RV32. However,
PMP address register format is still 32 bit wide.
Signed-off-by: Ivan Klokov
A series of patches that correct the conversion of virtual addresses
to physical ones. Correct exception for mbare mode and fix MXR bit
behavior with MPV\MPRV bits.
---
v2:
- Fix typo, specify the fixed commits
---
Ivan Klokov (2):
target/riscv/cpu_helper.c: Invalid exception on MMU
rrent
nominal privilege mode were set to MPP. vsstatus.MXR makes readable
those pages marked executable at the VS translation stage.
Fixes: 36a18664ba ("target/riscv: Implement second stage MMU")
Signed-off-by: Ivan Klokov
---
target/riscv/cpu_helper.c | 24
1 f
generates an access-fault
exception based on the pmp_violation flag only.
Fixes: 1448689c7b ("target/riscv: Allow specifying MMU stage")
Signed-off-by: Ivan Klokov
---
target/riscv/cpu_helper.c | 30 +++---
1 file changed, 7 insertions(+), 23 deletions(-)
di
A series of patches that correct the conversion of virtual addresses
to physical ones. Correct exception for mbare mode and fix MXR bit
behavior with MPV\MPV bits.
Ivan Klokov (2):
target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
target/riscv/cpu_helper.c: Fix mxr bit
generates an access-fault
exception based on the pmp_violation flag only.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu_helper.c | 30 +++---
1 file changed, 7 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index
rrent
nominal privilege mode were set to MPP. vsstatus.MXR makes readable
those pages marked executable at the VS translation stage.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu_helper.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_hel
Print RvV extension register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov
---
v5:
- Fix typo, move macros out of function, direct access to cfg.vlen field.
---
target/riscv/cpu.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion
Print RvV extesion register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov
---
v4:
- General part of patch has been merged, rebase riscv part and resend.
---
target/riscv/cpu.c | 56 +-
1 file changed, 55 insertions(+), 1 deletion
Since g_new is used to initialize the RISCVAPLICState->state structure,
in some case we get behavior that is not as expected. This patch
changes this to g_new0, which allows to initialize the APLIC in the correct
state.
Signed-off-by: Ivan Klokov
---
hw/intc/riscv_aplic.c | 2 +-
1 f
Print RvV extesion register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov
---
target/riscv/cpu.c | 56 +-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5bc0005cc7..cfd063a5dc
The patch added an ability to include VPU registers in the 'cpu' logging.
---
v3:
- split of the patch into two parts: general and RISC-V specific
---
Ivan Klokov (2):
util/log: Add vector registers to log
target/riscv: Add RVV registers to log
accel/tcg/cpu-exec.c | 3 +++
Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.
Signed-off-by: Ivan Klokov
---
accel/tcg/cpu-exec.c | 3 +++
include/hw/core/cpu.h | 2 ++
include/qemu/log.h| 1 +
util/log.c| 2 ++
4 files changed, 8 insertions(+)
diff --git a/accel/tcg/cp
Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular regs.
Signed-off-by: Ivan Klokov
---
v2:
- fix option name
- fix byte ordering
---
accel/tcg/cpu-exec.c | 3 +++
include/hw/core/cpu.h | 2 ++
include/qemu/log.h| 1 +
target/riscv/cpu
Hello guys. I would be really appreciate if you look this patch.It would be nice to merge it to new release 8.0 27.02.2023, 12:02, "Ivan Klokov" :The decoding of the slli_uw currently contains decodingerror: shamt part of opcode has six bits, not five.Fixes 3de1fb71("target/riscv:
т:
On Fri, 17 Feb 2023 07:45:14 PST (-0800), dbarb...@ventanamicro.com
wrote:
On 2/17/23 12:14, Ivan Klokov wrote:
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
The code was added by 02c1b569a15b4b06a so I believe a "Fixes:" tag
is in
order:
Fixes: 02c1b
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov
---
disas/riscv.c | 8
1 file changed, 4 insertions(+), 4
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Signed-off-by: Ivan Klokov
---
v2:
- added fixes line
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..d0639cd047 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular regs.
Signed-off-by: Ivan Klokov
---
accel/tcg/cpu-exec.c | 5 +
include/hw/core/cpu.h | 2 ++
include/qemu/log.h| 3 ++-
target/riscv/cpu.c| 49 ++-
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