Re: [PATCH] riscv: Add helper to make NaN-boxing for FP register

The patch description is modified and a new version is committed. -- Ian Jiang Richard Henderson 于2020年1月28日周二 上午1:38写道： > > On 1/27/20 6:10 AM, Ian Jiang wrote: > > The function that makes NaN-boxing when a 32-bit value is assigned > > to a 64-bit FP register is spl

[PATCH v2] riscv: Add helper to make NaN-boxing for FP register

The function that makes NaN-boxing when a 32-bit value is assigned to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). Then it is applied in translating of the FLW instruction. Signed-off-by: Ian Jiang --- target/riscv/insn_trans/trans_rvf.inc.c | 17 +++-- 1 file

Re: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing

Got it. As the first step, I just summit a new patch: [PATCH] riscv: Add helper to make NaN-boxing for FP register I'd like to carry out other fixes after this patch is reviewed. Richard Henderson 于2020年1月24日周五 上午2:53写道： > > On 1/22/20 6:05 PM, Ian Jiang wrote: > > But I am n

[PATCH] riscv: Add helper to make NaN-boxing for FP register

, FSUB.S and so on. Signed-off-by: Ian Jiang --- target/riscv/insn_trans/trans_rvf.inc.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index e23cd639a6..3bfd8881e7 100644 --- a

Re: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing

Richard Henderson 于2020年1月23日周四 上午11:07写道： > > On 1/22/20 2:48 PM, Ian Jiang wrote: > > Richard Henderson 于2020年1月23日周四 上午1:11写道： > >> > >> On 1/21/20 11:53 PM, Ian Jiang wrote: > >>> -- > >>> Ian Jiang > >>> > >>> Ri

Re: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing

Richard Henderson 于2020年1月23日周四 上午1:11写道： > > On 1/21/20 11:53 PM, Ian Jiang wrote: > > -- > > Ian Jiang > > > > Richard Henderson 于2020年1月22日周三 下午4:53写道： > >> > >> On 1/21/20 9:24 PM, Ian Jiang wrote: > >>> For FMV.W.X that moves

Re: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing

-- Ian Jiang Richard Henderson 于2020年1月22日周三 下午4:53写道： > > On 1/21/20 9:24 PM, Ian Jiang wrote: > > For FMV.W.X that moves the lower 32 bits of an integer register to a > > floating-point register, Rd should encoded with NoN-boxing scheme. > > Note: This applies to RV64

[PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing

For FMV.W.X that moves the lower 32 bits of an integer register to a floating-point register, Rd should encoded with NoN-boxing scheme. Note: This applies to RV64 only. Signed-off-by: Ian Jiang --- target/riscv/insn_trans/trans_rvf.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a

Re: [PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions

Just find that there is a previous patch at https://github.com/palmer-dabbelt/qemu/commit/a37f21c27d3e2342c2080aafd4cfe7e949612428 -- Ian Jiang Alistair Francis 于2020年1月21日周二 下午6:48写道： > > On Tue, Jan 21, 2020 at 8:08 PM Ian Jiang wrote: > > > > According to the RISC-V s

Re: riscv: How to check floating point support is currently enabled?

Alistair Francis 于2020年1月21日周二 下午6:50写道： > > On Tue, Jan 21, 2020 at 11:12 AM Ian Jiang wrote: > > > > The function riscv_cpu_fp_enabled() is used for checking whether floating > > point support is currently enabled. In fact it checks the FS field in the > > mst

[PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions

According to the RISC-V specification, when executing an MRET or SRET instruction, xPIE in mstatus or sstatus should be set to 1. The orginal QEMU does not give the right operations. This patch fix the problem. Signed-off-by: Ian Jiang --- target/riscv/op_helper.c | 4 ++-- 1 file changed, 2

riscv: How to check floating point support is currently enabled?

and bit 5) may be an better way. That is bool riscv_cpu_fp_enabled(CPURISCVState *env) if (env->misa & (MISA_F | MISA_F) { return true; } return false; } -- Ian Jiang

[PATCH] riscv: Fix defination of TW bits in mstatus CSR

The origin defination of TW bits in mstatus is not correct. This patch fixes the problem. Signed-off-by: Ian Jiang --- target/riscv/cpu_bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e99834856c..fb2e0b340e

[PATCH] riscv: Fix defination of csr operations

There is a mistake in defining CSR operations for pmpcfg registers. This patch fixes the bug. Signed-off-by: Ian Jiang --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da02f9f0b1..e07b5267be 100644 --- a

riscv: How to get more CSR information in debug trace?

0 mepc mcause I want more information of other CSRs, such as sstatus, misa, pmpconfig0. How to get debug trace on all CSRs defined in RISC-V specification? Thanks! -- Ian Jiang

riscv: How to debug a wrong pc after executing ret instruction?

00056c IN: 0x80003da0: 10503023 sd t0,256(zero) ... QEMU version === upstream tag v4.2.0 -- Ian Jiang