On Sat, Sep 7, 2024 at 9:44 AM maobibo wrote:
>
> Add huacai who is maintainer of Loongarch Linux kernel.
>
> On 2024/9/6 下午10:55, Jason A. Donenfeld wrote:
> > Hi,
> >
> > It appears that as of QEMU 9.1, it's possible to boot LoongArch machines
> > that don't provide EFI or ACPI.
> >
> > Would yo
On Wed, Jul 3, 2024 at 3:51 PM Jiaxun Yang wrote:
>
>
>
> 在2024年7月1日七月 下午2:57，Jiaxun Yang写道：
> > 在2024年5月30日五月 上午7:49，Bibo Mao写道：
> >> Loongson Binary Translation (LBT) is used to accelerate binary
> >> translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
> >> eflags (eflags) an
Hi, Jiaxun,
Rename loongarch_ipi to loongson_ipi? It will be shared by both MIPS
and LoongArch in your series.
Huacai
On Sun, May 21, 2023 at 6:24 PM Jiaxun Yang wrote:
>
> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
> Loongson 3A5000's IPI implementation have 4 mailboxes per
>
Reviewed-by: Huacai Chen
On Tue, Aug 30, 2022 at 7:39 AM Philippe Mathieu-Daudé wrote:
>
> Hi Alex,
>
> (+Aleksandar/Huacai)
>
> On 26/8/22 19:21, Alex Bennée wrote:
> > It's becoming harder to maintain a cross-compiler to test this host
> > architecture a
Hi, all,
On Fri, Aug 12, 2022 at 10:26 AM gaosong wrote:
>
> CC: Huacai Chen
>
> On 2022/8/11 下午9:24, Waldemar Brodkorb wrote:
> > Hi Qemu developers,
> >
> > I am trying to bootup a loongarch64 Linux kernel in Qemu 7.1.0-rc2.
> > The problem is I get no
Hi, Jiaxun,
I'm not familiar with TCG, please review, thanks.
Huacai
On Thu, Aug 19, 2021 at 6:09 AM Philippe Mathieu-Daudé wrote:
>
> Sorry, use Huacai's newer email .
>
> On Thu, Aug 19, 2021 at 12:07 AM Philippe Mathieu-Daudé
> wrote:
> >
> > Cc'ing Jiaxun & Huacai.
> >
> > On 8/18/21 10:1
Reviewed-by: Huacai Chen
On Mon, Aug 16, 2021 at 8:10 AM Philippe Mathieu-Daudé wrote:
>
> We already call check_cp1_enabled() earlier in the "pre-conditions"
> checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue.
> Remove the duplicated calls.
>
> Sig
Reviewed-by: Huacai Chen
On Fri, Aug 13, 2021 at 7:02 PM Philippe Mathieu-Daudé wrote:
>
> Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
> 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
> 48 virtual address bits in each 64-bit segment, not 40.
>
> Fixe
Reviewed-by: Huacai Chen
On Fri, Aug 13, 2021 at 7:01 PM Philippe Mathieu-Daudé wrote:
>
> Document the cores on which each Loongson-3A CPU is based (see
> commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
>
> Signed-off-by: Philippe Mathieu-Daudé
Hi, Philippe,
On Fri, Apr 9, 2021 at 5:36 PM Philippe Mathieu-Daudé wrote:
>
> Commit cd3a53b727d ("clock: Add clock_ns_to_ticks() function")
> removed the limitation of using clock with a frequency of 1 GHz
> or more.
>
> The previous commit converted the MIPS CP0 timer to use this
> new clock_n
Reviewed-by: Huacai Chen
On Sat, Feb 20, 2021 at 12:56 PM Jiaxun Yang wrote:
>
> 在 2021/2/20 上午1:38, Philippe Mathieu-Daudé 写道:
> > Restrit KVM to the following MIPS machines:
> > - malta
> > - loongson3-virt
> >
> > Signed-off-by: Philippe Mathieu
I think it can be removed.
Huacai
On Tue, Feb 9, 2021 at 12:40 AM Jiaxun Yang wrote:
>
>
>
> On Mon, Feb 8, 2021, at 3:39 AM, Thomas Bogendoerfer wrote:
> > On Wed, Feb 03, 2021 at 08:52:34PM +0800, Jiaxun Yang wrote:
> > >
> > >
> > > On Wed, Feb 3, 2021, at 8:34 PM, Thomas Bogendoerfer wrote:
Hi, Jiaxun,
On Mon, Jan 18, 2021 at 9:17 AM Jiaxun Yang wrote:
>
> Loongson IPI controller is a MMIO based simple level triggered
> interrupt controller. It will trigger IRQ to it's upstream
> processor when set register is written.
>
> It also has 4 64bit mailboxes to pass boot information to
>
Hi, Jiaxun,
On Mon, Jan 18, 2021 at 9:17 AM Jiaxun Yang wrote:
>
> loongson3_virt has KVM SMP support in kenrel.
s/kenrel/kernel/g
Huacai
> This patch adds TCG SMP support by enable IPI controller
> for machine.
>
> Also add definition about IRQs to enhance readability.
>
> Note that TCG SMP can
Reviewed-by: Huacai Chen
On Tue, Jan 12, 2021 at 9:25 AM Jiaxun Yang wrote:
>
> Per core ISR is a set of 32-bit registers spaced by 8 bytes.
> This patch fixed calculation of it's size and also added check
> of alignment at reading & writing.
>
> Signed-off-by: Ji
n 2021 at 21:11, Philippe Mathieu-Daudé
> >> wrote:
> >>>
> >>> From: Huacai Chen
> >>>
> >>> As suggested by Philippe Mathieu-Daudé, rework Loongson's liointc:
> >>> 1, Move macro definitions to loongson_lio
Reviewed-by: Huacai Chen
On Thu, Jan 7, 2021 at 2:46 AM Philippe Mathieu-Daudé wrote:
>
> The 'fulong2e' machine alias has been marked as deprecated since
> QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e').
> Time to remove it now.
>
>
Hi, Philippe and Peter,
On Tue, Jan 5, 2021 at 2:30 AM Philippe Mathieu-Daudé wrote:
>
> On 1/4/21 7:24 PM, Philippe Mathieu-Daudé wrote:
> > On 1/4/21 6:39 PM, Philippe Mathieu-Daudé wrote:
> >> On 1/4/21 4:01 PM, Peter Maydell wrote:
> >>> On Mon, 4 Jan 2021 at 13:59, Philippe Mathieu-Daudé
>
Reviewed-by: Huacai Chen
On Sat, Jan 2, 2021 at 7:17 AM Philippe Mathieu-Daudé wrote:
>
> On 1/1/21 9:42 PM, Philippe Mathieu-Daudé wrote:
> > On 12/15/20 7:45 AM, Jiaxun Yang wrote:
> >> It's useful for bootloader to do IO opreations.
> >>
> >> Signe
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/bonito.c b/hw/pci-
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Replace pci_set_byte(PCI_INTERRUPT_PIN) by
> pci_config_set_interrupt_pin().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 3 ++-
> 1 file changed, 2 i
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Use the PCI_DEVFN() macro to replace the '0x28' magic value,
> this way it is clearer we access PCI function #0 of slot #5.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
Reviewed-by: Huacai Chen
On Fri, Jan 1, 2021 at 6:49 AM Philippe Mathieu-Daudé wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/bonito.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.
Hi, BALATON
On Sun, Dec 27, 2020 at 9:21 AM BALATON Zoltan wrote:
>
> Compiling vt82c686.c fails without APM and ACPI_PM functions. Add
> dependency on these in Kconfig to fix this.
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/isa/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
Reviewed-by: Huacai Chen
On Tue, Dec 22, 2020 at 4:35 AM Philippe Mathieu-Daudé wrote:
>
> On 12/19/20 8:23 AM, Jiaxun Yang wrote:
> > highmem started from 0x2000.
>
> "started from" -> "starts at"?
>
> > Now we can have up to 2G RAM.
Reviewed-by: Huacai Chen
On Sun, Dec 20, 2020 at 1:52 AM Philippe Mathieu-Daudé wrote:
>
> On 12/19/20 8:12 AM, Jiaxun Yang wrote:
> > Websites are downing, but GitHub may last forever.
> > Loongson even doesn't recogonize 2E as their products nowadays..
> >
&
Reviewed-by: Huacai Chen
On Sun, Dec 20, 2020 at 2:23 AM Philippe Mathieu-Daudé wrote:
>
> On 12/19/20 8:21 AM, Jiaxun Yang wrote:
> > It was missed in 3ca7639ff00 ("hw/mips/fuloong2e:
> > Set CPU frequency to 533 MHz"), we need to tell kernel
> > correct clock
Reviewed-by: Huacai Chen
On Sat, Dec 19, 2020 at 3:22 PM Jiaxun Yang wrote:
>
> modetty and busclock is not handled by kernel and the parameter
> here seems unreasonable.
>
> Signed-off-by: Jiaxun Yang
> ---
> hw/mips/fuloong2e.c | 2 --
> 1 file changed, 2 deletion
Reviewed-by: Huacai Chen
On Sat, Dec 19, 2020 at 3:13 PM Jiaxun Yang wrote:
>
> Seems useless
>
> Fixes: 051c190bce5 ("MIPS: Initial support of fulong mini pc (machine
> construction)")
> Signed-off-by: Jiaxun Yang
> Reviewed-by: Philippe Mathieu-Daudé
&
Reviewed-by: Huacai Chen
On Tue, Dec 22, 2020 at 5:35 AM Willian Rampazzo wrote:
>
> On Sat, Dec 19, 2020 at 4:30 AM Jiaxun Yang wrote:
> >
> > The kernel comes from debian archive so it's trusted.
> >
> > Signed-off-by: Jiaxun Yang
> > ---
> &g
Reviewed-by: Huacai Chen
On Mon, Dec 14, 2020 at 8:32 AM Philippe Mathieu-Daudé wrote:
>
> Userland ELF binaries using Loongson SIMD instructions have the
> HWCAP_LOONGSON_MMI bit set [1].
> Binaries compiled for Loongson 3A [2] have the HWCAP_LOONGSON_EXT
> bit set for the LQ /
Daudé
> > ---
> > Based-on: <20201215125716.477023-1-chenhua...@kernel.org>
> > ---
> > MAINTAINERS | 1 +
> > tests/acceptance/machine_mips_loongson3v.py | 66 +
> > 2 files changed, 67 insertions(+)
>
Update MIPS machine documentation to add Loongson-3 based machine description.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
---
docs/system/target-mips.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/system/target-mips.rst b/docs/system/target
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19
u-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000
-kernel -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for
TCG/KVM automatically.
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by:
ed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
---
hw/intc/loongson_liointc.c | 36 +-
include/hw/intc/loongson_liointc.h | 22 ++
2 files changed, 38 insertions(+), 20 deletions(-)
create mode 100644 include/hw/intc/loongson_liointc.h
diff
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
MAINTAINERS
-by: Philippe Mathieu-Daudé .
V17 -> V18:
1, Remove merged patches;
2, Sync code with upstream;
3, Many improvements suggested by Philippe Mathieu-Daudé.
V18 -> V19:
1, Add related files to MAINTAINERS;
2, Some improvements suggested by Jiaxun Yang.
Huacai Chen and Jiaxun Yang (5):
hw/i
Yes, that's fine.
On Thu, Dec 17, 2020 at 2:11 AM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 12/15/20 1:57 PM, Huacai Chen wrote:
> > Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
> > UEFI-like interface for BIOS-Ker
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19
ed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
---
hw/intc/loongson_liointc.c | 36 +-
include/hw/intc/loongson_liointc.h | 22 ++
2 files changed, 38 insertions(+), 20 deletions(-)
create mode 100644 include/hw/intc/loongson_liointc.h
diff
-by: Philippe Mathieu-Daudé .
V17 -> V18:
1, Remove merged patches;
2, Sync code with upstream;
3, Many improvements suggested by Philippe Mathieu-Daudé.
Huacai Chen and Jiaxun Yang (5):
hw/intc: Rework Loongson LIOINTC
hw/mips: Implement fw_cfg_arch_key_name()
hw/mips: Add Loongson-3 boot
Update MIPS machine documentation to add Loongson-3 based machine description.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
---
docs/system/target-mips.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/system/target-mips.rst b/docs/system/target
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.c
u-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000
-kernel -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for
TCG/KVM automatically.
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
de
Hi, Philippe,
On Mon, Dec 14, 2020 at 9:49 PM Philippe Mathieu-Daudé wrote:
>
> On 12/14/20 3:37 AM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Mon, Dec 14, 2020 at 7:09 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 12/13/20 11:17 PM, Ph
Hi, Philippe,
On Mon, Dec 14, 2020 at 7:09 AM Philippe Mathieu-Daudé wrote:
>
> On 12/13/20 11:17 PM, Philippe Mathieu-Daudé wrote:
> > On 12/11/20 12:32 PM, Philippe Mathieu-Daudé wrote:
> >> On 12/11/20 3:46 AM, Huacai Chen wrote:
> >>> Hi, Rechard and Peter,
&
Hi, Rechard and Peter,
On Wed, Dec 2, 2020 at 5:32 PM Philippe Mathieu-Daudé wrote:
>
> On 12/2/20 2:14 AM, Huacai Chen wrote:
> > Hi, Phillippe,
> >
> > On Tue, Nov 24, 2020 at 6:25 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 11/6/20 5:
Use @kernel.org address as the main communications end point. Update the
corresponding M-entries and .mailmap (for git shortlog translation).
Signed-off-by: Huacai Chen
---
.mailmap| 2 ++
MAINTAINERS | 8
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/.mailmap b
Hi, Phillippe,
On Mon, Nov 30, 2020 at 6:08 PM Philippe Mathieu-Daudé wrote:
>
> On 11/28/20 7:19 AM, Huacai Chen wrote:
> > On Tue, Nov 24, 2020 at 4:52 AM Philippe Mathieu-Daudé
> > wrote:
> >> On 11/6/20 5:21 AM, Huacai Chen wrote:
> >>> As sugg
Hi, Phillippe,
On Tue, Nov 24, 2020 at 6:25 AM Philippe Mathieu-Daudé wrote:
>
> On 11/6/20 5:21 AM, Huacai Chen wrote:
> > Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
> > UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
> &
Hi, Philippe,
On Tue, Nov 24, 2020 at 5:54 AM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 11/6/20 5:21 AM, Huacai Chen wrote:
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently i
Hi, Philippe,
On Tue, Nov 24, 2020 at 6:24 AM Philippe Mathieu-Daudé wrote:
>
> On 11/23/20 9:52 PM, Philippe Mathieu-Daudé wrote:
> > On 11/6/20 5:21 AM, Huacai Chen wrote:
> >> As suggested by Philippe Mathieu-Daudé, rework Loongson's liointc:
> &g
Hi, Philippe,
On Tue, Nov 24, 2020 at 4:52 AM Philippe Mathieu-Daudé wrote:
>
> On 11/6/20 5:21 AM, Huacai Chen wrote:
> > As suggested by Philippe Mathieu-Daudé, rework Loongson's liointc:
> > 1, Move macro definitions to loongson_liointc.h;
> > 2, Remove magic
Reviewed-by: Huacai Chen
On Tue, Nov 24, 2020 at 6:42 PM Philippe Mathieu-Daudé wrote:
>
> Huacai, ping?
>
> On 5/12/20 9:09 AM, Philippe Mathieu-Daudé wrote:
> > +Paolo
> >
> > On 4/29/20 10:29 AM, Philippe Mathieu-Daudé wrote:
> >> This code must not
+CC Jiaxun
Hi, Jiaxun,
What do you think about?
Huacai
On Fri, Nov 20, 2020 at 6:55 PM Philippe Mathieu-Daudé wrote:
>
> On 11/20/20 5:28 AM, Huacai Chen wrote:
> > On Wed, Nov 18, 2020 at 1:17 AM Philippe Mathieu-Daudé
> > wrote:
> >> On 10/7/20 10:39 AM, Hua
Hi, Philippe,
On Wed, Nov 18, 2020 at 1:17 AM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 10/7/20 10:39 AM, Huacai Chen wrote:
> > After converting from configure to meson, KVM support is lost for MIPS,
> > so re-enable it in meson.build.
> >
> &
Hi, Philippe,
On Sat, Nov 7, 2020 at 8:11 PM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 11/6/20 5:21 AM, Huacai Chen wrote:
> > From: Jiaxun Yang
> >
> > Our current code assumed the target page size is always 4k
> > when handling PageMask and VPN2,
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19
Update MIPS machine documentation to add Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/target-mips.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
index cd2a931..138441b 100644
--- a
As suggested by Philippe Mathieu-Daudé, rework Loongson's liointc:
1, Move macro definitions to loongson_liointc.h;
2, Remove magic values and use macros instead;
3, Replace dead D() code by trace events.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
---
hw
u-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000
-kernel -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for
TCG/KVM automatically.
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
de
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.c
r Loongson-3's TCG mode;
4, Many other improvements suggested by Philippe Mathieu-Daudé.
V15 -> V16:
1, Remove some unused code;
2, Add Reviewed-by: Richard Henderson .
V16 -> V17:
1, Remove merged patches;
2, Rework Loongson LIOINTC;
3, Fix update_pagemask() for MIPS R6;
4, Add Revi
un Yang
Signed-off-by: Huacai Chen
---
target/mips/cp0_helper.c | 27 +--
target/mips/cpu.h| 1 +
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index 709cc9a..92bf14f 100644
--- a/target/mips/cp0
Hi, Phillippe,
On Tue, Nov 3, 2020 at 10:53 PM Philippe Mathieu-Daudé wrote:
>
> On 10/30/20 11:25 AM, Huacai Chen wrote:
> > From: Jiaxun Yang
> >
> > Our current code assumed the target page size is always 4k
> > when handling PageMask and VPN2, however, variabl
Hi, Philippe,
On Wed, Nov 4, 2020 at 4:23 AM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 10/30/20 11:25 AM, Huacai Chen wrote:
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently i
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.c
accel=tcg -cpu Loongson-3A1000
-kernel -append ...
Use QEMU with KVM:
qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000
-kernel -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for
TCG/KVM automatically.
Signed-off-
Update MIPS machine documentation to add Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/target-mips.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
index cd2a931..138441b 100644
--- a
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19
Loongson-3 processors.
Reviewed-by: Richard Henderson
Signed-off-by: Huacai Chen
---
target/mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f449758..470f59c 100644
--- a/target/mips/translate.c
+++ b
;
2, Fix malta breakage caused by variable page size;
3, Add unaligned access support for Loongson-3's TCG mode;
4, Many other improvements suggested by Philippe Mathieu-Daudé.
V15 -> V16:
1, Remove some unused code;
2, Add Reviewed-by: Richard Henderson .
Huacai Chen and Jiaxun Yang (8):
target
un Yang
Signed-off-by: Huacai Chen
---
target/mips/cp0_helper.c | 36 +---
target/mips/cpu.h| 1 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index 12143ac..d90ddd9 100644
--
Update MIPS machine documentation to add Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/target-mips.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
index cd2a931..138441b 100644
--- a
accel=tcg -cpu Loongson-3A1000
-kernel -append ...
Use QEMU with KVM:
qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000
-kernel -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for
TCG/KVM automatically.
Signed-off-
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.c
Loongson-3 processors.
Signed-off-by: Huacai Chen
---
target/mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f449758..470f59c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31442,8
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19
;
2, Fix malta breakage caused by variable page size;
3, Add unaligned access support for Loongson-3's TCG mode;
4, Many other improvements suggested by Philippe Mathieu-Daudé.
Huacai Chen and Jiaxun Yang (8):
target/mips: Fix PageMask with variable page size
target/mips: Add unaligned access supp
un Yang
Signed-off-by: Huacai Chen
---
target/mips/cp0_helper.c | 36 +---
target/mips/cpu.h| 1 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index 12143ac..d90ddd9 100644
--
Hi, Philippe,
On Sat, Oct 17, 2020 at 11:58 PM Philippe Mathieu-Daudé wrote:
>
> On 10/16/20 8:51 AM, Huacai Chen wrote:
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently it can work with
&g
Hi, Philippe,
On Fri, Oct 16, 2020 at 10:24 PM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 10/16/20 8:51 AM, Huacai Chen wrote:
> > Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
> > UEFI-like interface for BIOS-Kernel boot parameters)
Hi, Philippe,
On Fri, Oct 16, 2020 at 11:15 PM Philippe Mathieu-Daudé wrote:
>
> On 10/16/20 8:51 AM, Huacai Chen wrote:
> > From: Jiaxun Yang
> >
> > Our current code assumed the target page size is always 4k
> > when handling PageMask and VPN2, however, variabl
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
---
hw/mips/fw_cfg.c| 35 +++
hw/mips/fw_cfg.h| 19 +++
hw/mips
ub.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang
Signed-off-by: Huacai Chen
---
target/mips/translate.c | 179
1 file changed, 179 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25321d3c
Add Loongson-3A CPU models and Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/cpu-models-mips.rst.inc | 10 --
docs/system/target-mips.rst | 10 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/docs/system/cpu-models
GPR
gssdrc1: similar to sdr but RT is FPR instead of GPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang
Signed-off-by: Huacai Chen
---
target/mips/translate.c | 178 +
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.c | 162 +++
hw/mips/loongson3_bootp.h
accel=tcg -cpu Loongson-3A1000
-kernel -append ...
Use QEMU with KVM:
qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000
-kernel -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for
TCG/KVM automatically.
Signed-off-
c1: load 16 bytes to FPR
gssqc1: store 16 bytes from FPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang
Signed-off-by: Huacai Chen
---
target/mips/translate.c | 86 +
1 fil
ways LE).
V12 -> V13:
1, Sync code with upstream;
2, Re-enable KVM support for MIPS in meson;
V13 -> V14:
1, Remove merged patches;
2, Split boot parameter helpers to a separate patch;
4, Many other improvements suggested by Philippe Mathieu-Daudé.
Huacai Chen and Jiaxun Yang (8):
target/mips:
un Yang
Signed-off-by: Huacai Chen
---
target/mips/cp0_helper.c | 36 +---
target/mips/cpu.h| 1 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index de64add038..f3478d826b 100644
--
Hi, Philippe,
On Tue, Oct 13, 2020 at 9:45 PM Philippe Mathieu-Daudé wrote:
>
> On 10/13/20 1:12 PM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Mon, Oct 12, 2020 at 4:12 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 10/11/2
Hi, Philippe,
On Mon, Oct 12, 2020 at 4:12 PM Philippe Mathieu-Daudé wrote:
>
> On 10/11/20 4:53 AM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Sat, Oct 10, 2020 at 5:09 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Hi Huacai,
> >&g
Hi, Philippe,
On Sun, Oct 11, 2020 at 7:13 PM Philippe Mathieu-Daudé wrote:
>
> On 10/11/20 5:02 AM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Sat, Oct 10, 2020 at 9:07 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 10/7/20 10:3
Hi, Philippe,
On Sat, Oct 10, 2020 at 9:07 PM Philippe Mathieu-Daudé wrote:
>
> On 10/7/20 10:39 AM, Huacai Chen wrote:
> > From: Jiaxun Yang
> >
> > LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
> > group of instructions
Hi, Philippe,
On Sat, Oct 10, 2020 at 5:09 PM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 10/7/20 10:39 AM, Huacai Chen wrote:
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently i
Hi, Philippe,
On Fri, Oct 9, 2020 at 11:29 PM Philippe Mathieu-Daudé wrote:
>
> Hi Huacai,
>
> On 10/7/20 10:39 AM, Huacai Chen wrote:
> > Add Loongson-3A CPU models and Loongson-3 based machine description.
> >
> > Signed-off-by: Huacai Chen
> > ---
>
Add Loongson-3A CPU models and Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/cpu-models-mips.rst.inc | 10 --
docs/system/target-mips.rst | 10 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/docs/system/cpu-models
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