[PATCH v5 1/6] target/riscv: Add svukte extension capability variable

ayout. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..d8771

[PATCH v5 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu

[PATCH v5 5/6] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/c

[PATCH v5 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 4 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v5 4/6] target/riscv: Check memory access to meet svukte rule

. Depend on Sv39 and check virtual addresses bit[SXLEN-1] 5. Raises a page-fault exception corresponding to the original access type. Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files Signed-off-by: Frank Chang Signed-off-by: Fea.Wang Signed-off-by: Daniel Henrique Barboza Reviewed

[PATCH v5 6/6] target/riscv: Check svukte is not enabled in RV32

The spec explicitly says svukte doesn't support RV32. So check that it is not enabled in RV32. Signed-off-by: Fea.Wang --- target/riscv/tcg/tcg-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..3b99c

[PATCH v5 0/6] Introduce svukte ISA extension

w the riscv,isa order [v2] * Refactor the code [v1] * Add svukte extension Fea.Wang (6): target/riscv: Add svukte extension capability variable target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Support hstatus[HUKTE] bit when svukte extensi

[PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu

[PATCH v4 0/6] Introduce svukte ISA extension

* Add svukte extension Fea.Wang (6): target/riscv: Add svukte extension capability variable target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled target/riscv: Check memory access to meet s

[PATCH v4 1/6] target/riscv: Add svukte extension capability variable

ayout. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..d8771

[PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule

. Depend on Sv39 and check virtual addresses bit[SXLEN-1] 5. Raises a page-fault exception corresponding to the original access type. Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files Signed-off-by: Frank Chang Signed-off-by: Fea.Wang Signed-off-by: Daniel Henrique Barboza Reviewed

[PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32

Based on the spec, svukte depends on SV39, so it should not be enabled in RV32. Signed-off-by: Fea.Wang --- target/riscv/tcg/tcg-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..4273f1f472 100644 --- a

[PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 4 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v4 5/6] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/c

[PATCH 1/1] hw/net: Support Marvell 88E1111 phy driver

ear phydev->link and stop the flow. To avoid getting stuck, change the constant return value in QEMU for the bit to 1 to keep the driver going. Signed-off-by: Fea.Wang --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/xilinx_axienet.c b/h

[PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu

[PATCH v3 5/5] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..6d3e9d563d 10

[PATCH v3 0/5] Introduce svukte ISA extension

riscv-isa-manual/pull/1564 base-commit: 27652f9ca9d831c67dd447346c6ee953669255f0 [v3] * Fix some typos * Refine code by separating a function into two dedicated functions. * Follow the riscv,isa order [v2] * Refactor the code [v1] * Add svukte extension Fea.Wang (5): target/riscv: Add s

[PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 4 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 385a2c67c2..4b9f899217 100644

[PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule

. Depend on Sv39 and check virtual addresses bit[SXLEN-1] 5. Raises a page-fault exception corresponding to the original access type. Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files Signed-off-by: Frank Chang Signed-off-by: Fea.Wang Signed-off-by: Daniel Henrique Barboza Reviewed

[PATCH v3 1/5] target/riscv: Add svukte extension capability variable

ayout. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..d8771ca641 100644 --- a/target/

[PATCH v2 4/5] target/riscv: Check memory access to meet svuket rule

4. Depend on Sv39 and check virtual addresses bit[SXLEN-1] 5. Raises a page-fault exception corresponding to the original access type. Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files Signed-off-by: Frank Chang Signed-off-by: Fea.Wang Reviewed-by: Jim Shu --- target/riscv

[PATCH v2 5/5] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..69187c9aa1 10

[PATCH v2 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu

[PATCH v2 1/5] target/riscv: Add svukte extension capability variable

ayout. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..d8771ca641 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_

[PATCH v2 0/5] Introduce svukte ISA extension

riscv-isa-manual/pull/1564 * Refactor the code base-commit: 27652f9ca9d831c67dd447346c6ee953669255f0 [v1] * Add svukte extension Fea.Wang (5): target/riscv: Add svukte extension capability variable target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Su

[PATCH v2 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 4 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 385a2c67c2..4b9f899217 100644 --- a/target/riscv/cpu_bits.h +++ b

[PATCH 0/1] Keep transaction attribute in address_space_map()

The follow-up transactions may use the data in the attribution, so keep the value of attribution from the function parameter. Fea.Wang (1): softmmu/physmem.c: Keep transaction attribute in address_space_map() system/physmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.34.1

[PATCH 1/1] softmmu/physmem.c: Keep transaction attribute in address_space_map()

The follow-up transactions may use the data in the attribution, so keep the value of attribution from the function parameter just as flatview_translate() above. Signed-off-by: Fea.Wang --- system/physmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/physmem.c b

[PATCH 0/5] Introduce svukte ISA extension

ayout. base-commit: 8d0a03f689bff16c93df311fdd724c2736d28556 * Add svukte extension Fea.Wang (5): target/riscv: Add svukte extension capability variable target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Support hstatus[HUKTE] bit when svukte extensi

[PATCH 4/5] target/riscv: Check memory access to meet svuket rule

4. Depend on Sv39 and check virtual addresses bit[SXLEN-1] 5. Raises a page-fault exception corresponding to the original access type. Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files Signed-off-by: Frank Chang Signed-off-by: Fea.Wang Reviewed-by: Jim Shu --- target/riscv

[PATCH 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu

[PATCH 5/5] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fc3f75e826..a568194317 10

[PATCH 1/5] target/riscv: Add svukte extension capability variable

ayout. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 96fe26d4ea..636b12e1c2 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_

[PATCH 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 4 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7e3f629356..54c3ae0a4e 100644 --- a/target/riscv/cpu_bits.h +++ b

[PATCH v3 1/3] hw/dma: Enhance error handling in loading description

is one of the possible ways to handle it. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- hw/dma/xilinx_axidma.c | 30 ++ 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 0ae056ed06..ad307994c2

[PATCH v3 2/3] hw/dma: Add a trace log for a description loading failure

Due to a description loading failure, adding a trace log makes observing the DMA behavior easy. Signed-off-by: Fea.Wang Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang --- hw/dma/trace-events| 3 +++ hw/dma/xilinx_axidma.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw

[PATCH v3 0/3] hw/dma: Add error handling for loading descriptions failing

format for an unsigned variable base-commit: d82f37faf5643897b2e61abb229499d64a51aa26 [v2] * Add DMASR_DECERR case * Squash the two commits to one base-commit: 915758c537b5fe09575291f4acd87e2d377a93de [v1] base-commit: 1806da76cb81088ea026ca3441551782b850e393 Fea.Wang (3): hw/dma: Enhance error

[PATCH v3 3/3] hw/net: Fix the transmission return size

Fix the transmission return size because not all bytes could be transmitted successfully. So, return a successful length instead of a constant value. Signed-off-by: Fea.Wang Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1 insertion

[PATCH v4 5/6] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv

[PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec

From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h

[PATCH v4 2/6] target/riscv: Define macros and variables for ss1p13

Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 4 insertions(+), 1

[PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++ 2 files changed, 33 insertions(+) diff --gi

[PATCH v4 3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 +

[PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec

changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (5): target/riscv: Define macros and variables for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Ad

[PATCH v4 6/6] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +- target/riscv/tcg/tcg-cpu.c | 4 2 files changed, 9 insertions(+), 1 deletion(-) diff

[PATCH v2 2/3] hw/dma: Add a trace log for a description loading failure

Due to a description loading failure, adding a trace log makes observing the DMA behavior easy. Signed-off-by: Fea.Wang Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang --- hw/dma/trace-events| 3 +++ hw/dma/xilinx_axidma.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw

[PATCH v2 0/3] hw/dma: Add error handling for loading descriptions failing

case * Squash the two commits to one base-commit: 915758c537b5fe09575291f4acd87e2d377a93de [v1] base-commit: 1806da76cb81088ea026ca3441551782b850e393 Fea.Wang (3): hw/dma: Enhance error handling in loading description hw/dma: Add a trace log for a description loading failure hw/net: Fix the

[PATCH v2 3/3] hw/net: Fix the transmission return size

Fix the transmission return size because not all bytes could be transmitted successfully. So, return a successful length instead of a constant value. Signed-off-by: Fea.Wang Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1 insertion

[PATCH v2 1/3] hw/dma: Enhance error handling in loading description

is one of the possible ways to handle it. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- hw/dma/xilinx_axidma.c | 30 ++ 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 0ae056ed06..ad307994c2

[PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv

[PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 2 files changed, 9

[PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec

From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h

[PATCH v3 3/6] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +- target/riscv/tcg/tcg-cpu.c | 4 2 files changed, 9 insertions(+), 1 deletion(-) diff

[PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++ 2 files changed, 33 insertions(+) diff --gi

[PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec

menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (5): target/riscv: Define macros and variables for ss1p13 target/riscv: Support the version for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN

[PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13

Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target

[PATCH 3/4] hw/dma: Add a trace log for a description loading failure

Due to a description loading failure, adding a trace log makes observing the DMA behavior easy. Signed-off-by: Fea.Wang --- hw/dma/trace-events| 3 +++ hw/dma/xilinx_axidma.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw/dma/trace-events b/hw/dma/trace-events index 3c47df54e4

[PATCH 4/4] hw/net: Fix the transmission return size

Fix the transmission return size because not all bytes could be transmitted successfully. So, return a successful length instead of a constant value. Signed-off-by: Fea.Wang --- hw/net/xilinx_axienet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/xilinx_axienet.c b

[PATCH 1/4] hw/dma: Enhance error handling in loading description

Loading a description from memory may cause a bus-error. In this case, the DMA should stop working, set the error flag, and return the error value. Signed-off-by: Fea.Wang --- hw/dma/xilinx_axidma.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/dma

[PATCH 2/4] hw/dma: Break the loop when loading descriptions fails

When calling the loading a description function, it should be noticed that the function may return a failure value. Breaking the loop is one of the possible ways to handle it. Signed-off-by: Fea.Wang --- hw/dma/xilinx_axidma.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff

[PATCH 0/4] hw/dma: Add error handling for loading descriptions failing

: 1806da76cb81088ea026ca3441551782b850e393 Fea.Wang (4): hw/dma: Enhance error handling in loading description hw/dma: Break the loop when loading descriptions fails hw/dma: Add a trace log for a description loading failure hw/net: Fix the transmission return size hw/dma/trace-events | 3

[RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec

From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv

[RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (4): target/riscv: Support the version for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Ad

[RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/ta

[RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 2 files changed, 9

[RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files

[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/ta

[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 2 files changed, 9

[PATCH 2/5] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec

From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv

[PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (4): target/riscv: Support the version for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Ad

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

From: Jim Shu Public the conversion function of priv_spec and string in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 3 +++ target/riscv/tcg/tcg

[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index

[PATCH 2/5] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files changed, 13 insertions(+), 2 deletions(-) diff

[PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f888025c59

[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 ++ 2 files changed, 11 insertions(+) di

[PATCH 0/5] target/riscv: Support RISC-V privilege 1.13 spec

requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (4): target/riscv: Support the version for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Ad