A bit late to the party, but still
Tested-by: Evgeny Iakovlev
On 1/23/2023 17:41, Philippe Mathieu-Daudé wrote:
On 23/1/23 17:23, Peter Maydell wrote:
On Mon, 23 Jan 2023 at 15:21, Philippe Mathieu-Daudé
wrote:
pl011_can_receive() returns the number of bytes that pl011_receive()
can
accept, pl011_can_transmit() returns a boolean.
I was thinking of:
, also do some sanity checking on
untrusted incoming input state.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 3fa3b75d04..05e8bdc050 100644
--- a/hw/char/pl011.c
+++ b/hw/char
RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
---
hw/char/pl011.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
based on review feedback.
v2:
* Moved FIFO depth refactoring part of FIFO flags change into its own
commit.
* Added a reset method for PL011
Evgeny Iakovlev (5):
hw/char/pl011: refactor FIFO depth handling code
hw/char/pl011: add post_load hook for backwards-compatibility
hw/char/pl011
.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 36 +++-
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index c15cb7af20..28ba242e2f 100644
--- a/hw
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011
(albeit guest-invisible) side-effect of this change is
that previously we would always increment s->read_pos in UARTDR read
handler even if FIFO was disabled, now we are limiting read_pos to not
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
Signed-off-by: Evgeny Iakov
On 1/23/2023 16:59, Evgeny Iakovlev wrote:
On 1/23/2023 16:21, Philippe Mathieu-Daudé wrote:
On 23/1/23 15:43, Evgeny Iakovlev wrote:
On 1/23/2023 09:14, Philippe Mathieu-Daudé wrote:
On 20/1/23 16:54, Evgeny Iakovlev wrote:
UART should be enabled in general and have RX enabled
On 1/23/2023 16:21, Philippe Mathieu-Daudé wrote:
On 23/1/23 15:43, Evgeny Iakovlev wrote:
On 1/23/2023 09:14, Philippe Mathieu-Daudé wrote:
On 20/1/23 16:54, Evgeny Iakovlev wrote:
UART should be enabled in general and have RX enabled specifically
to be
able to receive data from
On 1/23/2023 09:14, Philippe Mathieu-Daudé wrote:
On 20/1/23 16:54, Evgeny Iakovlev wrote:
UART should be enabled in general and have RX enabled specifically to be
able to receive data from peripheral device. Same goes for transmitting
data to peripheral device and a TXE flag.
Check if UART
On 1/20/2023 19:22, Peter Maydell wrote:
On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
Previous change slightly modified the way we handle data writes when
FIFO is disabled. Previously we kept incrementing read_pos and were
storing data at that position, although we only have a
single
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 33
AZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1
registers in the same way the rest of DCM is currently done. Do account
for access traps though with access_tda.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
---
target/arm/debug_helper.c | 21 +
1 file ch
registers
* Patch 3 is dropped because it was manually picked into target-arm.next
Evgeny Iakovlev (2):
target/arm: implement DBGCLAIM registers
target/arm: provide stubs for more external debug registers
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 54
some sanity checking on
untrusted incoming input state.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 3fa3b75d04..4df649a064 100644
--- a/hw/char/pl011.c
(albeit guest-invisible) side-effect of this change is
that previously we would always increment s->read_pos in UARTDR read
handler even if FIFO was disabled, now we are limiting read_pos to not
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
Signed-off-by: Evgeny Iakov
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 4df649a064..f9413f3703 100644
--- a/hw/char/pl011.c
.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
---
hw/char/pl011.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index c72fbb7d50..dd20b76609 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -54,6 +54,11
.
* Added a reset method for PL011
Evgeny Iakovlev (5):
hw/char/pl011: refactor FIFO depth handling code
hw/char/pl011: add post_load hook for backwards-compatibility
hw/char/pl011: implement a reset method
hw/char/pl011: better handling of FIFO flags on LCR reset
hw/char/pl011: check if
RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index f9413f3703..c72fbb7d50
On 1/17/2023 18:00, Eric Auger wrote:
Hi Evgeny,
On 1/16/23 16:37, Evgeny Iakovlev wrote:
Hi!
We are using qemu-tcg-aarch64 to run Hyper-V test and debug builds for
arm. Besides some minor fixes that i have submitted over the last
couple of weeks, one big compatibility item for us is SMMUv3
On 1/17/2023 16:48, Richard Henderson wrote:
On 1/17/23 05:04, Evgeny Iakovlev wrote:
+ { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
+ .access = PL1_RW, .accessfn = access_tda,
+
On 1/19/2023 14:45, Peter Maydell wrote:
On Tue, 17 Jan 2023 at 22:05, Evgeny Iakovlev
wrote:
PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.
Current code open-codes a bunch of depth-dependent logic
On 1/19/2023 14:30, Peter Maydell wrote:
On Tue, 17 Jan 2023 at 22:05, Evgeny Iakovlev
wrote:
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag
On 1/19/2023 14:27, Peter Maydell wrote:
On Tue, 17 Jan 2023 at 22:05, Evgeny Iakovlev
wrote:
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions
(albeit guest-invisible) side-effect of this change is
that previously we would always increment s->read_pos in UARTDR read
handler even if FIFO was disabled, now we are limiting read_pos to not
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
Signed-off-by: Evgeny Iakov
v2:
* Moved FIFO depth refactoring part of FIFO flags change into its own
commit.
* Added a reset method for PL011
Evgeny Iakovlev (4):
hw/char/pl011: refactor FIFO depth handling code
hw/char/pl011: implement a reset method
hw/char/pl011: better handling of FIFO flags on LCR reset
hw
.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 3184949d69..522f36e4f3 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -54,6 +54,11 @@
#define INT_E (INT_OE
RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 404d52a3b8..3184949d69 100644
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 329cc6926d..404d52a3b8 100644
--- a/hw/char/pl011.c
On 1/17/2023 16:24, Peter Maydell wrote:
On Fri, 6 Jan 2023 at 17:28, Evgeny Iakovlev
wrote:
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual flag update will happen
AZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1
registers in the same way the rest of external debug is currently done.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
---
target/arm/debug_helper.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/targe
-arm.next
Evgeny Iakovlev (2):
target/arm: implement DBGCLAIM registers
target/arm: provide stubs for more external debug registers
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 59 +++
2 files changed, 60 insertions(+)
--
2.34.1
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
---
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 38 ++
2
Hi!
We are using qemu-tcg-aarch64 to run Hyper-V test and debug builds for
arm. Besides some minor fixes that i have submitted over the last couple
of weeks, one big compatibility item for us is SMMUv3 2-stage
translations support. We can do fine without it right now, but having it
would als
On 1/13/2023 14:20, Peter Maydell wrote:
On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev
wrote:
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
uses a valid mask to clear unsupported SCR_EL3
On 1/6/2023 17:28, Peter Maydell wrote:
On Fri, 6 Jan 2023 at 15:44, Alex Bennée wrote:
Peter Maydell writes:
The semihosting API, at least for Arm, has a modeflags string so the
guest can say whether it wants to open O_BINARY or not:
https://github.com/ARM-software/abi-aa/blob/main/semihos
.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 9108ed2be9..fcc2600944 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -54,6 +54,11 @@
#define INT_E (INT_OE
Evgeny Iakovlev (2):
hw/char/pl011: better handling of FIFO flags on LCR reset
hw/char/pl011: check if UART is enabled before RX or TX operation
hw/char/pl011.c | 51 ++---
include/hw/char/pl011.h | 5 +++-
2 files changed, 41 insertions(+), 15
(and RXFF to be cleared) after resetting FIFO will just
hang.
Correctly reset FIFO flags on FIFO reset. Also, clean up some FIFO
depth handling code based on current FIFO mode.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 35 +--
include/hw/char
On 1/6/2023 10:48, Bin Meng wrote:
On Fri, Jan 6, 2023 at 3:39 PM Philippe Mathieu-Daudé wrote:
On 5/1/23 22:19, Evgeny Iakovlev wrote:
Windows open(2) implementations opens files in text mode by default and
needs a Windows-only O_BINARY flag to open files as binary. Qemu already
s/Qemu
On 1/6/2023 10:48, Bin Meng wrote:
On Fri, Jan 6, 2023 at 3:39 PM Philippe Mathieu-Daudé wrote:
On 5/1/23 22:19, Evgeny Iakovlev wrote:
Windows open(2) implementations opens files in text mode by default and
needs a Windows-only O_BINARY flag to open files as binary. Qemu already
s/Qemu
: Evgeny Iakovlev
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
semihosting/syscalls.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c
index 508a0ad88c..b621d78c2d 100644
--- a/semihosting/syscalls.c
+++ b
Windows open(2) implementations opens files in text mode by default and
needs a Windows-only O_BINARY flag to open files as binary. Qemu already
knows about that flag in osdep.h, so we can just add it to the
host_flags for better compatibility when running qemu on Windows.
Signed-off-by: Evgeny
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Helps Hyper-V boot on aarch64-tcg because it context-switches DBGCLAIM
on EL2 entry/exit.
Signed-off-by: Evgeny Iakovlev
---
target/arm/cpu.h | 1 +
target/arm
T_HCX is
enabled and exposed to the guest. As a result EL3 writes of that bit are
ignored.
Signed-off-by: Evgeny Iakovlev
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bac2ea62c4..962affdd52 100644
--- a/targe
e way the rest of DCM is currently done. Do
account for access traps though with access_tda.
Signed-off-by: Evgeny Iakovlev
---
target/arm/debug_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index b244e146e2..2a7c3
Small series of changes to aarch64 emulation to better support running
Hyper-V as a TCG guest wtih EL3 firmware.
Evgeny Iakovlev (3):
target/arm: implement DBGCLAIM registers
target/arm: provide RAZ/WI stubs for more DCC registers
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX
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