Reviewed-by: Eric Johnson
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel
Reviewed-by: Eric Johnson
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel
Reviewed-by: Eric Johnson
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel
Reviewed-by: Eric Johnson
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel
Hi Petar,
When Config5 exists, Config4 must exist. So it wouldn't be reserved anymore.
You change does not seem to set Config3.M or Config4.M either. They must be
set when Config5 is present.
Eric
-Original Message-
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[mailt
Hi Yongbok,
You need to make Status.MX writeable as well.
- .CP0_Status_rw_bitmask = 0x3678FF1F,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
-Eric
> -Original Message-
> From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
> [mailto:qemu-devel-
> bounces+eric.johnson=
On 02/15/2013 03:41 PM, Anthony Liguori wrote:
Happy hacking!
Regards,
Anthony Liguori
We might want to update the planning section of
http://wiki.qemu.org/Contribute/StartHere to link to 1.4 and 1.5.
I don't think I have a Wiki account otherwise I would just fix it myself.
-Eric
Clear the DSP hflags at the start of compute_hflags. Otherwise access
is not properly disabled once enabled.
Signed-off-by: Eric Johnson
---
target-mips/cpu.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 31602ac..5963d62
9a40 100644
--- a/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
+++ b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
@@ -9,8 +9,8 @@ int main()
rs = 0xBC0123AD;
rt = 0x01643721;
-resulth = 0x04;
-resultl = 0xD751F050;
+resulth = 0x05;
+resultl = 0xE72F050;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
Reviewed-by: Eric Johnson
the list of CPUMIPSStates. */
static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
Reviewed-by: Eric Johnson
VERFLOW;
@@ -2681,7 +2687,7 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env,
uint32_t fst0)
set_float_rounding_mode(float_round_down,&env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0,&env->active_fpu.fp_status);
-RESTORE_ROUNDING_MODE;
+restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
& (float_flag_invalid | float_flag_overflow)) {
wt2 = FP_TO_INT32_OVERFLOW;
Reviewed-by: Eric Johnson
On 01/03/2013 10:50 AM, Richard Henderson wrote:
On 01/03/2013 10:39 AM, Eric Johnson wrote:
While making this change please keep in mind that newer MIPS32
processors allow more than 31 bits of user address space (up to 3.5
GiB) if they have Enhanced Virtual Address support.
Interesting.
Well
On 01/03/2013 09:24 AM, Alexander Graf wrote:
On 03.01.2013, at 18:19, Peter Maydell wrote:
On 3 January 2013 13:17, Alexander Graf wrote:
MIPS only supports 31 bits of virtual address space for user space, so let's
make sure we stay within that limit with our preallocated memory block.
This
The call to gen_logic_imm for OPC_LUI passes -1 for rs. This
causes the MIPS_DEBUG statement to seg fault due to the deference
of regnames[rs]. This patch fixes that.
Signed-off-by: Eric Johnson
---
target-mips/translate.c | 18 +++---
1 files changed, 11 insertions(+), 7
When MIPS_DEBUG_DISAS is defined the gen_logic_imm, gen_slt_imm,
gen_cond_move, gen_logic and gen_slt functions cause errors because ctx
is not defined. Fixed the functions by passing in the DisasContext.
Signed-off-by: Eric Johnson
---
target-mips/translate.c | 72
The microMIPS SWP and SDP instructions do not modify GPRs. So their
behavior is well defined when RD equals BASE. The MIPS Architecture
Verification Programs (AVPs) check that they work as expected. This
is required for AVPs to pass.
Signed-off-by: Eric Johnson
---
target-mips/translate.c
The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level. These changes are needed
to pass the AVP suite.
Signed-off-by: Eric Johnson
---
target-mips/translate.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff
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