How to simulate a microcontroller whose ROM and RAM are the same address
space?
Some microcontrollers have a Haval architecture. ROM and RAM have separate
buses, which means they have the same address space, such as 0-0x100. How
do I set the memory region?
Thanks!
I simulate an MCU firmware.
This firmware uses USB peripherals and is a function of a USB flash drive.
QEMU can well support the operation of instructions, but I don't know how
to extend the function of a USB so that the USB flash drive can be
connected to the host.
I have checked some qemu docume
Many SOCs have unique id, which is a fixed string of bytes.
I use "memory_region_init_ram" and "memory_region_add_subregion" to
simulate this region, how can I initialize specific bytes to fill?
thks~~~
Got it.
Peter Maydell 于2021年9月8日周三 下午5:47写道：
> On Wed, 8 Sept 2021 at 03:50, Duo jia wrote:
> > Also I want to know how to make a delay in qemu.
> > For example, when I send a UART data, there is a certain time interval
> from setting the register to when the data is sent.
于2021年9月7日周二 下午8:20写道：
> On Tue, 7 Sept 2021 at 12:28, Duo jia wrote:
> >
> > In the controller, QEMUTimer will be used in the implementation of timer
> simulation.
> >
> > I wrote an auto-loading timer with a period of 1ms and the clock source
> used is QEMU_C
In the controller, QEMUTimer will be used in the implementation of timer
simulation.
I wrote an auto-loading timer with a period of 1ms and the clock source
used is QEMU_CLOCK_VIRTUAL. But it doesn't seem to be very accurate,
because the actual time after I accumulated it to 500 times took about
7
Sept 2021 at 11:54, Duo jia wrote:
> >
> > I do some support on STM8 arch, the reference manual link is:
> >>
> >>
> https://www.st.com/resource/en/reference_manual/cd00218714-stm8l050j3-stm8l051f3-stm8l052c6-stm8l052r8-mcus-and-stm8l151l152-stm8l162-stm8al31-stm8a
w：
[image: image.png]
I don't kown when to check the "PENDING" because I can't get the when
interrrupt exec over.
Is there a similar implementation in qemu？
Peter Maydell 于2021年9月3日周五 下午6:25写道：
> On Fri, 3 Sept 2021 at 09:33, Duo jia wrote:
> >
> > I und
I understand the hardware，but How to achieve this function with qemu？，
For example, this interrupt is not allowed to be nested. When the new
interrupt comes, how can I detect that the interrupt is executing?
Peter Maydell 于2021年9月2日周四 下午3:43写道：
> On Thu, 2 Sept 2021 at 03:18, Duo jia wr
HI,
I has two QOM model，A and B， When A‘s register changed，B’s register will
should also be change .
I dont konw how to change B's reg in A device .
rupt_request &= ~CPU_INTERRUPT_RESET;
> }
> if (interrupt_request & CPU_INTERRUPT_HARD) {
> if(env->intsrc != 0){
> idx = ctz32(env->intsrc);
> env->intsrc &= ~(1<
> cs->interrupt_request &= ~CPU_INTERR
Thank you for the detailed explanation.
Peter Maydell 于2021年8月6日周五 下午6:16写道：
>
> On Fri, 6 Aug 2021 at 07:24, Duo jia wrote:
> > I am simulating a device. When an interrupt occurs, another interrupt
> > comes, and the second interrupt will not be triggered because the
>
I am simulating a device. When an interrupt occurs, another interrupt
comes, and the second interrupt will not be triggered because the
first interrupt has not yet finished.
I want to know whether qemu can detect whether the interrupt has been
executed, will there be a callback here?
Or how can I
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