: Davidson Francis
---
target/i386/cpu.c | 8 +++-
target/i386/gdbstub.c | 15 +--
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5253399459..65bdc48cc0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
ffort required
to debug i8086 code, avoiding workarounds with architecture XML files,
and proper instruction disassembly and stack dumps out-of-the-box.
Kind regards,
Davidson Francis.
tiveness would be limited.
Ref:
[1]: https://gist.github.com/Theldus/4e1efc07ec13fb84fa10c2f3d054dccd
Kind regards,
Davidson Francis.
Hello,
Thanks for working on this, your tree works fine here and the issue
seems to be fixed, I have nothing to complain about.
Regards,
Davidson Francis.
On 01-07-2018 05:18, Stafford Horne wrote:
Hello,
We have been working on a few patches to fixed QEMU for OpenRISC and I
included the
On 07-06-2018 12:56, Richard Henderson wrote:
On 06/07/2018 06:27 AM, Davidson Francis wrote:
Dear all,
Currently Qemu supports only 2 cores when SMP enabled for or1k architecure, so
I would like to know if there is a quick way to increase the number of cores by
changing a few lines of code or
cause I'll start working with the SMP feature and
it would be great to use Qemu with more than two cores.
Kind regards,
Davidson Francis.
Thank you for quick reply,
Yes, I've tried, after that, the register works as expected, but even so, if I
enable the interrupts right after, I still receive interrupts from the same IRQ,
but maybe there is something wrong with my code.
Regards,
Davidson Francis.
2018-05-19 23:54 GMT-
