[PATCH v5 1/1] target/riscv: Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32

[PATCH v5 0/1] target/riscv: Add Zihintpause support

the trans_pause function v2 -> v3 No changes, v2 was lost from the list v3 -> v4 No longer break the reservation in trans_pause v4 -> v5 Rabase on top of https://github.com/alistair23/qemu/tree/riscv-to-apply.next Dao Lu (1): Add Zihintpause support target/riscv/cpu.c

Re: [PATCH v4 1/1] target/riscv: Add Zihintpause support

Will do, thanks! Dao On Wed, Jul 20, 2022 at 10:31 PM Alistair Francis wrote: > > On Tue, Jul 19, 2022 at 4:02 AM Dao Lu wrote: > > > > ping > > Sorry for the delay. > > Do you mind rebasing this on > https://github.com/alistair23/qemu/tree/riscv-to-apply.nex

Re: [PATCH v4 1/1] target/riscv: Add Zihintpause support

ping On Tue, Jul 5, 2022 at 10:49 AM Dao Lu wrote: > > Added support for RISC-V PAUSE instruction from Zihintpause extension, > enabled by default. > > Tested-by: Heiko Stuebner > Signed-off-by: Dao Lu > --- > target/riscv/cpu.c | 2

[PATCH v4 0/1] target/riscv: Add Zihintpause support

the trans_pause function v2 -> v3 No changes, v2 was lost from the list v3 -> v4 No longer break the reservation in trans_pause Dao Lu (1): Add Zihintpause support target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn

[PATCH v4 1/1] target/riscv: Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7

Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support

That sounds reasonable to me. Will change in the next version. Thanks, Dao On Sun, Jun 26, 2022 at 10:13 PM Alistair Francis wrote: > > On Wed, Jun 22, 2022 at 2:17 AM Dao Lu wrote: > > > > From what I know that's generally the way reservations are handled: >

Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support

lways do that). So this is legal, as would be not breaking the reservation. I don't have a strong opinion on this and am fine about changing it if anyone does. Thanks, Dao On Mon, Jun 20, 2022 at 4:39 PM Alistair Francis wrote: > > On Thu, Jun 9, 2022 at 2:42 PM Dao Lu wrote: > >

[PATCH v3 0/1] target/riscv: Add Zihintpause support

USE macro inside the trans_pause function v2 -> v3 No changes, v2 was lost from the list Dao Lu (1): Add Zihintpause support target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++- target

[PATCH v3 1/1] target/riscv: Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7

Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support

Please ignore, I have missed the commit message, will resend a v3. Sorry about that. Dao On Tue, Jun 7, 2022 at 8:44 PM Dao Lu wrote: > > Tested-by: Heiko Stuebner > Signed-off-by: Dao Lu > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h

[PATCH v3 1/1] target/riscv: Add Zihintpause support

Tested-by: Heiko Stuebner Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++- target/riscv/insn_trans/trans_rvi.c.inc | 18 ++ 4 files changed, 27

[PATCH v3 0/1] target/riscv: Add Zihintpause support

USE macro inside the trans_pause function v2 -> v3 No changes, v2 was lost from the list Dao Lu (1): Add Zihintpause support target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++- target

Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support

Hi Alistair, Thanks for the response. I don't think I can find any comments on this patch though, could you help point me to them? Thanks, Dao On Tue, Jun 7, 2022 at 4:04 PM Alistair Francis wrote: > > On Wed, Jun 8, 2022 at 8:59 AM Dao Lu wrote: > > > > Ping > &g

Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support

Ping On Tue, May 24, 2022 at 1:36 PM Dao Lu wrote: > > Tested-by: Heiko Stuebner > Signed-off-by: Dao Lu > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 7 ++- >

Re: [PATCH 1/1] Add Zihintpause support

); +gen_set_pc_imm(ctx, ctx->pc_succ_insn); +tcg_gen_exit_tb(NULL, 0); +ctx->base.is_jmp = DISAS_NORETURN; return true; } I will wait a bit to see if there are any more comments. On Tue, May 10, 2022 at 8:43 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 5/

[PATCH 0/1] Add Zihintpause support

Tested along with pause support added to cpu_relax function for linux, the changes I made to linux to test can be found here: https://github.com/dlu42/linux/tree/pause_support_v1 Dao Lu (1): Add Zihintpause support target/riscv/cpu.c | 2 ++ target/riscv/cpu.h

[PATCH 1/1] Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld by default. Signed-off-by: Dao Lu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++- target/riscv/insn_trans