/ftkbc010.c
@@ -0,0 +1,214 @@
+/*
+ * Faraday FTKBC010 emulator for A369.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ *
+ * Written by Dante Su
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+#in
@@
+/*
+ * QEMU model of ROM
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in th
file mode 100644
index 000..eb68bc6
--- /dev/null
+++ b/hw/ftspi020.c
@@ -0,0 +1,338 @@
+/*
+ * Faraday FTSPI020 Flash Controller
+ *
+ * Copyright (c) 2012 Faraday Technology
+ *
+ * Written by Dante Su
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw.h"
+#inclu
file mode 100644
index 000..61ce495
--- /dev/null
+++ b/hw/ftssp010.c
@@ -0,0 +1,526 @@
+/*
+ * QEMU model of the FTSSP010 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
new file mode 100644
index 000..0eb4e83
--- /dev/null
+++ b/hw/ftnandc021.c
@@ -0,0 +1,528 @@
+/*
+ * QEMU model of the FTNANDC021 NAND Flash Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any
file mode 100644
index 000..2f5552e
--- /dev/null
+++ b/hw/fttsc010.c
@@ -0,0 +1,239 @@
+/*
+ * Faraday FTTSC010 emulator.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ *
+ * Written by Dante Su
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw.h"
+#include &qu
.c
new file mode 100644
index 000..006fcae
--- /dev/null
+++ b/hw/ftsdc010.c
@@ -0,0 +1,360 @@
+/*
+ * QEMU model of the FTSDC010 MMC/SD Host Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any
/ftrtc011.c
@@ -0,0 +1,308 @@
+/*
+ * QEMU model of the FTRTC011 RTC Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the
/ftwdt010.c
@@ -0,0 +1,224 @@
+/*
+ * QEMU model of the FTWDT010 WatchDog Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the
/ftpwmtmr010.c b/hw/ftpwmtmr010.c
new file mode 100644
index 000..357e758
--- /dev/null
+++ b/hw/ftpwmtmr010.c
@@ -0,0 +1,226 @@
+/*
+ * Faraday FTPWMTMR010 Timer.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ *
+ * Written by Dante Su
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include
Faraday Technology
+ * Written by Dante Su
+ *
+ * This code is licensed under the GNU LGPL
+ */
+
+#include "sysbus.h"
+#include "ui/console.h"
+#include "framebuffer.h"
+#include "ui/pixel_ops.h"
+
+#include "ftlcdc200.h"
+
+enum ftlcdc
/fti2c010.c
new file mode 100644
index 000..3073314
--- /dev/null
+++ b/hw/fti2c010.c
@@ -0,0 +1,209 @@
+/*
+ * QEMU model of the FTSSP010 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person
/ftintc020.c
@@ -0,0 +1,342 @@
+/*
+ * Faraday FTINTC020 Programmable Interrupt Controller.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ *
+ * Written by Dante Su
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw.h"
+#include "sysbus.h"
+
+typedef struct {
+
new file mode 100644
index 000..2841455
--- /dev/null
+++ b/hw/ftdmac020.c
@@ -0,0 +1,625 @@
+/*
+ * QEMU model of the FTDMAC020 DMA Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Note: The FTDMAC020 decreasing address mode is not implemented
new file mode 100644
index 000..ab264dd
--- /dev/null
+++ b/hw/ftmac110.c
@@ -0,0 +1,567 @@
+/*
+ * QEMU model of the FTMAC110 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
/ftapbbrg020.c
new file mode 100644
index 000..3378312
--- /dev/null
+++ b/hw/ftapbbrg020.c
@@ -0,0 +1,485 @@
+/*
+ * QEMU model of the FTAPBBRG020 DMA Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Note: The FTAPBBRG020 DMA decreasing address mode is not
/ftgmac100.c
new file mode 100644
index 000..d66c719
--- /dev/null
+++ b/hw/ftgmac100.c
@@ -0,0 +1,621 @@
+/*
+ * QEMU model of the FTGMAC100 Controller
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su
+ *
+ * Permission is hereby granted, free of charge, to any person
,499 @@
+/*
+ * Faraday A369 Evalution Board
+ *
+ * Copyright (c) 2012 Faraday Technology
+ *
+ * Written by Dante Su
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "sysbus.h"
+#include "arm-misc.h"
+#include "devices.h"
+#include "net/net.h"
+#include &q
Faraday processors are a series of ARMv4/ARMv5TE clone.
* ARMv4 series (FA526, FA626).
All of them are now out-of-date, so I have no plan for them.
* ARMv5TE series (FA606TE, FA626TE, FA616TE, FA726TE)
All the single core RISC listed above are included in this patch.
And there are two
CODEC.
+ *
+ * base is wm8750.c
+ *
+ * Copyright (c) 2013 Faraday Technology
+ * Written by Dante Su
+ *
+ * This file is licensed under GNU GPL.
+ */
+
+#include "hw.h"
+#include "i2c.h"
+#include "audio/audio.h"
+
+#define IN_PORT_N2
+#define OUT_PORT_N1
+
+#defi
The s->addr is supposed to be reset along with the s->addrlen,
or it might be contains the previous address at last address cycle,
and causes problem to nand erase operation.
Signed-off-by: Kuo-Jung Su
---
hw/nand.c |1 +
1 file changed, 1 insertion(+)
diff --git a/hw/nand.c b/hw/nand.c
ind
The status register coding for BUSY/READY(BIT6)
is actually [Busy:0, Ready:1].
BTW, this patch not only apply the bug fix to status bit,
but also update the Busy/Ready status upon nand flash read/write/erase.
Signed-off-by: Kuo-Jung Su
---
hw/nand.c | 16 +++-
1 file changed, 15 in
Atmel, SST and Intel/Numonyx serial flash tend to power up
with the software protection bits set.
And thus the new m25p80.c in linux kernel would always tries
to use WREN(0x06) + WRSR(0x01) to turn-off the protection.
The WEL(0x02) of status register is supposed to be cleared
after WRSR(0x01).
Ther
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