On Fri, Sep 30, 2011 at 10:36 AM, Richard Henderson wrote:
> On 09/30/2011 12:12 AM, Jan Kiszka wrote:
>>> Breakpoint 1, __ldb_mmu (addr=1001716, mmu_idx=0)
>>> at /home/rth/work/qemu/qemu/softmmu_template.h:86
>>> 86 {
>>> (gdb) where
>>> #0 __ldb_mmu (addr=1001716, mmu_idx=0)
>>> at /
abi cc1, not an arm-none-linux-gnueabi
cc1. In my case that was useful because there was no dynamic memory
allocation. We also rely on semihosting for GCC testing.
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From: Daniel Jacobowitz
This patch improves ARM semihosting to the point where qemu-system-arm
can simulate cc1 from GCC. It can't simulate GCC itself, which
requires POSIXy bits like execve, but the backend works, including the
preprocessor.
* Use -kernel and -append for SYS_GET_CM
signed target_argv, defined in main. And
> target_argv is freed in main before starting simulation...
Well, that's possible - but that code was there already; I only moved
the CONFIG_USER_ONLY case down a couple of lines.
I don't recall why there's user-mode support in this file.
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From: Daniel Jacobowitz
This patch improves ARM semihosting to the point where qemu-system-arm
can simulate cc1 from GCC. It can't simulate GCC itself, which
requires POSIXy bits like execve, but the backend works, including the
preprocessor.
* Use -kernel and -append for SYS_GET_CM
h. I don't have any preference which
is applied, although I'm always in favor of eliminating unnecessary
recursive invocations.
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From: Daniel Jacobowitz
With enough parallelism, make will run all the dependencies of
build-all at the same time:
build-all: config-host.h config-all-devices.h $(DOCS) $(TOOLS)
So some of the $(TOOLS) will build before config-host.h is finished.
The object files need to depend on it
8. The code you've posted looks wrong.
IIRC there were some older ARM processors with a different value.
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On Wed, Feb 13, 2008 at 04:52:22PM +0100, Marius Groeger wrote:
> On Wed, 13 Feb 2008, Daniel Jacobowitz wrote:
>
> > On Wed, Feb 13, 2008 at 09:46:44AM +0100, Marius Groeger wrote:
> > > if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
if (ctx->sf_mode)
> gen_op_b_T1_64();
> else
> #endif
> gen_op_b_T1();
> if (ctx->singlestep_enabled)
> gen_op_debug()
> }
>
> It seems to me that the second if (ctx->singlestep_enabled) is
> rendundant.
No, if you've gone to a differ
gh I don't know if there is silicon to match yet.
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on
> the implementation.
If folks don't like the target conditionals there, I recommend we just
set some low bit to be sure it's a NaN and move on. The softfloat
implementation is not all that close to matching any one hardware FPU.
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t we need to make sure at least one mantissa
bit is set. If we're confident that the common NaN format will
already have some bit other than the qnan/snan bit set, this is fine;
otherwise, we might want to forcibly set some other mantissa bit.
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able the warning. It wasn't
an accidental decision on the kernel maintainers' part either.
I don't see the PVR read in current glibc, but I thought it was there;
I don't remember exactly what happened.
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e no idea of what's going wrong with this register and what should be
> its value.
Are you running recent Alpha binaries? I believe the unique register
is used for the thread-local storage base address.
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On Thu, Oct 18, 2007 at 06:57:19AM -0700, Boy Dfx wrote:
> From what I can see instructions are loaded from memory without a
> clock cycle penalty, but I wanted to be sure.
Yes. Qemu is absolutely useless for performance questions about
real hardware; it does not model any cycles.
--
act as preprocessing directives, the behavior is undefined."
GCC did not support it until here:
http://gcc.gnu.org/ml/gcc-patches/2002-02/msg01874.html
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ivate dynticks, just commenting the entry in
> alarm_timers structure. Since then, I can notice that the emulated
... and I think you're talking about a qemu option with the same name.
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d depends completely on the current processor
mode. It has nothing to do with the address.
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> TASK_SIZE border or something??
It makes more sense if you realize it's kernel/user mode not address
space.
> 2.) the MMUSUFFIX macro ("mmu" / "cmmu") what does this stand for??
cmmu is used to read code to execute, IIRC (different permissions).
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On Mon, Sep 24, 2007 at 04:05:45PM +0200, Andreas Schwab wrote:
> Daniel Jacobowitz <[EMAIL PROTECTED]> writes:
>
> > Glibc's test-float failed on my qemu testing. I tracked it down to
> > these routines: if you count the bits carefully, you'll see that
> &g
On Thu, Sep 20, 2007 at 06:28:25PM +0100, Thiemo Seufer wrote:
> It fixed an internal testcase, I'll have to check what was going
> on there, probably tomorrow.
I don't suppose you've had a chance to look at this?
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but now it's a quiet
NaN if the input was a quiet NaN so exp10(NaN) no longer raises
Invalid.
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--- fpu/softfloat-specialize.h (revision 182529)
+++ fpu/softfloat-specialize.h (local)
@@ -120,9 +120,7 @@ static commonNaNT float32ToCommonNaN( fl
static
nearest, return an signed appropriate signed zero. Why?
The MIPS ISA docs say a rounded result is returned in this case, and
that's what's in FST2 if that code is removed.
This shows up in the mul-subnormal-single-1.c test from GCC's ieee.exp.
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ike breakpoints to arbitrarily apply across all virtual
> address spaces.
I think they already do. Specific example, please.
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in copy_to_user_page...
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On Fri, Apr 20, 2007 at 02:22:09PM -0400, Daniel Jacobowitz wrote:
> I have an idea. When I was talking to Paul about breakpoints
> recently, I noticed something very strange in the ARM port: it
> continues to disassemble the instruction under a breakpoint after
> generating the deb
ongnu.org/archive/html/qemu-devel/2007-05/msg00037.html
Someone might want to try:
http://lists.nongnu.org/archive/html/qemu-devel/2007-04/msg00514.html
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p. What happens if you add an extra +1
to the translation block size if there's a breakpoint, in
target-mips/translate.c?
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: { *(.rodata) } > bios
+.rodata: { *(.rodata*) } > bios
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On Mon, Apr 16, 2007 at 06:01:04PM +0300, Blue Swirl wrote:
> I stand corrected. Is there anything that can be done to reduce this waste?
For a BIOS image, you might be OK with ld -N - that should suppress
the padding.
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; Nice theory (and I missed the modulo arithmetic, sorry), but on
> Ultrasparc the page sizes available are 8k, 64k, 4M and 256M.
#define ELF_MAXPAGESIZE 0x10
BFD and GNU ld think it's 1MB.
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oot d
> Obviously, it doesn't work (it always asked for a kernel image).
> I have already experienced a net-install through qemu for i386 target. Is
> this
> possible with an ARM target?
See Aurelien's walkthrough for this:
http://www.aurel32.net/info/debian_arm_qemu.php
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On Wed, Mar 28, 2007 at 03:00:08PM +0100, Paul Brook wrote:
> On Wednesday 28 March 2007 03:21, Daniel Jacobowitz wrote:
> > On Wed, Mar 28, 2007 at 12:35:18AM +0100, Thiemo Seufer wrote:
> > > Right, a piggyback-style loader would likely fail in that case.
> >
> > Wh
cetera, but the Forth interpreter is completely missing. Therefore,
so is the Forth console.
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thing to do. Or always putting the initrd at
the top of emulated RAM.
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compressed kernel image and initrd, but what matters is the size it
gets uncompressed to.
I don't remember any more than that so I'm sorry if it's total
garbage, which it might be. I did write a patch to stick the initrd
right after the loaded kernel; it didn't work a
.rdz}).
When I talked to Fabrice about this he recommended looking at what
other loaders (lilo, grub) do to avoid overwriting the kernel. I've
been meaning to do that for months but never got around to it.
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the same. The console doesn't stop updating
earlier in the boot, so something is a tiny bit happier, but cuda
still gets stuck.
-M prep: doesn't check for ADB, so doesn't hang there. Crashes later.
Not sure where, GDB couldn't backtrace far enough.
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On Fri, Mar 09, 2007 at 10:02:25AM -0500, Daniel Jacobowitz wrote:
> Has anyone tried to run OpenBSD/macppc on qemu?
>
> As far as I can tell the latest is that OpenHack'Ware says it doesn't
> support compressed ELF. I was going to work on that, but I can't get
>
ause I built it with GCC 4.x and I had to
make a couple of fixes that suggest it's used to older compilers and
binutils... I'll try some older tools next.
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h
This removes the MIPS_USES_FPU compilation time option, and replaces by a
> runtime one.
>
> Please comment.
Do you have any idea what performance effect this does (or doesn't)
have?
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n & (1 << 23)))
val = -val;
+val += extra;
if (val != 0)
gen_op_addl_T1_im(val);
} else {
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re not to complain about rw COW images
based on readonly ones...
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S:EIP=f180:f0001f77 SS:SP=:f00c6df0
Is there something I could try that would be more informative?
[It got there much quicker than without kqemu though! :-)]
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On Sat, Jan 20, 2007 at 05:44:30PM -, priya sridhar wrote:
> Is there no other way to run threaded applications using an emulator
> for ARM? system level emulation is possible?
That works just fine.
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__
n on the
command line (i.e. the override effectively happens after the +=).
You'd need to leave CFLAGS for the overrideable bits unless you
wanted to override all the += deliberately.
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On Mon, Nov 13, 2006 at 02:30:27PM -0500, Daniel Jacobowitz wrote:
> I was trying to run GDB remote debug tests through a -redir socket
> today. It crawled unbelievably. Paul guessed that slirp wasn't using
> TCP_NODELAY, and Nagle was to blame.
>
> He was even righter
hich seems a little counter intuitive.
No. Those are I/O device accesses, not memory accesses. Look at the
softmmu code instead.
It may be easiest to add some new instrumentation in the translation
code for whatever target you're interested in.
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ere.
> > >
> > > mount -o loop does this.
> >
> > How is everybody missing the point? :-) mount -o loop doesn't mount
> > qcow images.
> >
> Would be that difficult to write a qcow fs module ?
Probably not, but I think using nbd for it is much nicer.
ssing the files inside QEMU disk
> > images locally, without having to launch a virtual machine and accessing
> > then from there.
>
> mount -o loop does this.
How is everybody missing the point? :-) mount -o loop doesn't mount
qcow images.
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___
umbers" when checking the
> initramfs, both with a compressed ext2 filesystem image and with a
> compressed cpio archive. What am I doing wrong?
I don't know, but I'll be interested to find out. I tried two
different kernels on Debian amd64, and one of them could load an initrd
but
On Mon, Nov 13, 2006 at 02:30:27PM -0500, Daniel Jacobowitz wrote:
> I was trying to run GDB remote debug tests through a -redir socket
> today. It crawled unbelievably. Paul guessed that slirp wasn't using
> TCP_NODELAY, and Nagle was to blame.
>
> He was even righter
See trivial attached
patch.
Is this going to bite other things, i.e. does it need to be
configurable?
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---
slirp/tcp.h |2 +-
slirp/tcp_subr.c |2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
Index: qemu/slirp/
On Sun, Nov 12, 2006 at 07:02:55PM +0100, Dirk Behme wrote:
> Daniel Jacobowitz wrote:
> >This is with all of the patches I've posted to the
> >list applied
>
> If patches settle down would be nice to get a list of
> patches or a summary patch to be applied in which
On Sun, Nov 12, 2006 at 11:56:35AM -0500, Daniel Jacobowitz wrote:
> ---
> target-mips/cpu.h |3 ++-
> target-mips/exec.h |1 +
> target-mips/helper.c|2 +-
> target-mips/mips-defs.h |1 +
> target-mips/
ime for soft-mmu routines and tb management routines, which
is very good. Then there's about 65% executing guest code and the rest
in translation, virtual hardware, and other overhead.
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---
target-mips/cpu.h |3 ++-
target-mips/exec.h |1 +
On Sun, Nov 12, 2006 at 10:07:15AM -0500, Daniel Jacobowitz wrote:
> > Actually that gives me an idea. When a TLB entry with a different ASID gets
> > evicted we currently flush that page. This should be a no-op because we
> > already did a full flush when the ASID changed.
instead of a boost. I don't see anything
obvious that I could do about it, though. The qemu tlb table only has
room for is_user and the virtual address.
> Actually that gives me an idea. When a TLB entry with a different ASID gets
> evicted we currently flush that page. This shou
On Sun, Nov 05, 2006 at 10:38:20AM -0500, Daniel Jacobowitz wrote:
> On Mon, Mar 06, 2006 at 02:59:29PM +, Thiemo Seufer wrote:
> > Hello All,
> >
> > this patch vastly improves TLB performance on MIPS, and probably also
> > on other architectures. I measured
BIOS support, so I made the reset vector reload any
specified kernel and initrd. Works in my Debian rootfs; very handy for
automated benchmarking.
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---
hw/mips_r4k.c | 144 +---
target-mips/cpu.h |
doubt it would lead to any problems at all; and it
would be a localized change in two places in the GDB stub.
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> usefulness.
I'd recommend the even simpler hack of having qemu report a PC that
included the segment base :-)
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On Thu, Nov 09, 2006 at 12:57:29AM +0100, Marcel Kilgus wrote:
> Daniel Jacobowitz wrote:
> >> Leaving that aside, if I do set the breakpoint correctly at virtual
> >> address (e.g.) 0xC0123456 qemu will (correctly I guess) cause an
> >> exception for code offset 0x12
s.
> So all in all GDB just doesn't seem to cope very well with segmented
> memory.
Correct. It doesn't know anything at all about i386 segmentation.
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h
xes
- A usable kernel .config, the attached may help
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#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.19-rc3
# Sat Nov 4 11:53:04 2006
#
CONFIG_MIPS=y
#
# Machine selection
#
# CONFIG_MIPS_MTX1 is not set
# CONF
range. */
> +memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
>
> #if !defined(CONFIG_SOFTMMU)
> if (addr < MMAP_AREA_END)
>
>
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tx, EXCP_CpU, 3);
break;
+#if defined (CONFIG_USER_ONLY)
+case 0x1F:
+ if (ctx->opcode == 0x7c03e83b) /* rdhwr v1,$29 */
+ {
+ gen_op_tls_value ();
+ gen_op_store_T0_gpr_gpr3 ();
+ break;
+ }
+ /* Fall through to RI. */
+#endif
+
#if defined (TARGET_MIPS64)
ement whetever relocation it's complaining
> about.
This is dyngen we're talking about - presumably that isn't the bit that
needs to be PIC? Looks to me like the op file was compiled with the
PIC CFLAGS.
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laining that it couldn't find a fn for a given ip address.
I can confirm that this patch is correct - I have a bit for bit
identical copy in my working directory (I tend to batch on submitting
things...).
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Q
> increment
This is an unrelated problem, and much easier to fix. Don't increment
casts.
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On Thu, Jul 20, 2006 at 11:04:01PM +0200, Fabrice Bellard wrote:
> Daniel Jacobowitz wrote:
> >On Wed, Jul 19, 2006 at 08:43:57AM +, Steve Ellenoff wrote:
> >
> >>#3) Anytime I try to dump the instruction at the current IP such as:
> >>(gdb) x /10i $eip
>
the binary file
> itself? Everything I've read so far on GDB (and especially any GDB Gui
> front end) seems to suggest it's not possible. That would really suck.
Sure you can. It will just work.
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shows address 0x8180 for the first example.
>
> Maybe "b *0xbfc00380" works for your case. If it does, your mips-gdb
> is somehow strange.
This means that GDB has (mistakenly) decided that the first assembly
instruction in the function is part of a standard f
oal is of course not to conflict
with later versions of GDB.
And thanks for doing this! What a great idea!
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I even compiled
and ran the sample -> no exception.
Oh, damn! tmp is not the result, T0 is the result. No wonder this
didn't make any sense. I apologize, I'm really batting zero today.
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On Fri, Apr 28, 2006 at 04:51:39PM +0200, Dirk Behme wrote:
> Daniel Jacobowitz wrote:
> >I haven't tested the patched qemu, but I did test the expressions
> >themselves in standalone code, and they definitely do not detect
> >overflow.
>
> Maybe you can test Ralf&
ect, EXCP_OVERFLOW);
> }
tmp ^ T1 -> result and T1 of different sign
tmp ^ T0 -> result and T0 of different sign
Which implies that the operands have the same sign. Again, this case
can't overflow.
I haven't tested the patched qemu, but I did
-bit and 64-bit
targets uses different qemu binaries.
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de by Toshiba. It seems to me that MIPS is just as realistic and
> usable platform as ARM. But I would be very interested to hear from
> anyone who knows better.
>
> Now, I wonder when Qemu will support MIPS emulation? :-)
Good question. How about... last year?
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On Wed, Mar 22, 2006 at 02:45:11PM -0600, Troy Benjegerdes wrote:
> On Sat, Mar 11, 2006 at 02:57:03PM -0500, Daniel Jacobowitz wrote:
> > On Wed, Mar 08, 2006 at 10:55:21AM -0600, Troy Benjegerdes wrote:
> > > The only think I can track down so far is that BITS_PER_LONG is onl
On Thu, Mar 23, 2006 at 05:10:07PM +0100, Dirk Behme wrote:
> (gdb) s
> Cannot find bounds of current function
> (gdb) n
> Cannot find bounds of current function
Try using "si" and "ni" to step a single instruction. But make sure
you can run it before you try to
gt; code?
I've just been disabling USB support by a local patch and hoping
someone else fixed this :-)
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the program flow was changed */
Didn't we go round this recently? do_interrupt might modify
env->interrupt_request - see target-arm/helper.c for instance.
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#x27;d need
a few patches that were merged later; I haven't touched that build tree
since Nov. 27th.
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been merged into the main project?
Did you even look at the same page Paul sent you to? :-) It's active,
CVS works fine, and he's the author.
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atches have to be applied?
You have to select QEMU as your machine type when you configure the
kernel. Use the linux-mips.org CVS, of course.
> >(B) I have no idea if that method works with MIPS qemu; I only tested
> >-kernel.
>
> Hmm?
>
> I didn't quite understand
he MIPS QEMU.
(B) I have no idea if that method works with MIPS qemu; I only tested
-kernel.
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s the magic bullet? Any boot options that I need to give
> to the kernel? (BTW, I am calling the emulation as
>
> qemu-system-arm -kernel integratorcp.zImage -initrd arm_root.imfg
> -nographic -net user )
-net nic -net user, or no -net option at all. You need a network card
on
uch device or address
> #
>
> Any ideas?
Try -net nic -net user. Or no -net option at all; this should be the
default if no -net options are specified, IIRC.
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That's all the atomicity you need; the
instruction is being restarted after the base register was clobbered.
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On Sun, Dec 18, 2005 at 10:42:16AM -0700, M. Warner Losh wrote:
> In message: <[EMAIL PROTECTED]>
> Daniel Jacobowitz <[EMAIL PROTECTED]> writes:
> : On Sun, Dec 18, 2005 at 04:51:02PM +, Paul Brook wrote:
> : > Something like the attached patch.
> :
ood (averaging
about 10K/s - 30K/s most of the time, but occasionally spiking higher),
but there may be something we can do about that later. Thanks.
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h
someone'll get around to emulating the Integrator/AP,
which has a PCI bus, and then we can do it normally.
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Index: qemu/hw/smc91c111.c
===
--- qemu.orig/hw/smc91c111.c2005-12-13 19:3
sion of
> this program (usage: "./termslave /dev/pts/4" for example once qemu is
> running). If someone could tell me the name of THE unix-ish program to
> do the job, I would be glad to throw mine away.
It's probably just a line or two of 'expect
On Mon, Dec 05, 2005 at 08:50:46PM +0100, Fabrice Bellard wrote:
> Daniel Jacobowitz wrote:
> >Fabrice, since the last combined patch I sent you, I've dropped the exec.c
> >bits; added EXCP_HALTED; improved the unaligned access traps; and shaved
> >two
> >bits
ing bits merged.
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Index: cpu-exec.c
===
RCS file: /cvsroot/qemu/qemu/cpu-exec.c,v
retrieving revision 1.69
diff -u -p -r1.69 cpu-exec.c
--- cpu-exec.c 4 Dec 2005 18:46:05 - 1.69
+++ cp
x27;re supposed to configure applications
to use the correct compiler if they need a particular version. For
qemu that's --cc. Not so hard, was it?
--
Daniel Jacobowitz
CodeSourcery, LLC
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