[PATCH v10 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

...@embecosm.com/ - v9: https://lore.kernel.org/all/20250109152833.75385-1-craig.blackm...@embecosm.com/ Cc: Richard Henderson Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: Weiwei Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Craig

[PATCH v10 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 95 +--- 1 file changed, 87 insertions(+), 8 deletions(-) diff

[PATCH v9 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Craig Blackmore (1): target/riscv: rvv: Use wider accesses for unit stride load/store target/riscv/vector_helper.c | 92 1 file changed, 84 insertions(+), 8 deletions(-) -- 2.43.0

[PATCH v9 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 92 1 file changed, 84 insertions(+), 8 deletions(-) diff

[PATCH v8 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

-craig.blackm...@embecosm.com/ Cc: Richard Henderson Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: Weiwei Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Craig Blackmore (1): target/riscv: rvv: Use wider accesses for unit stride load/store

[PATCH v8 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 90 1 file changed, 82 insertions(+), 8 deletions(-) diff

[PATCH v7 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 107 +-- 1 file changed, 101 insertions(+), 6 deletions(-) diff

[PATCH v7 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

...@embecosm.com/ - v6: https://lore.kernel.org/all/20241218142937.1028602-1-craig.blackm...@embecosm.com/ Cc: Richard Henderson Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: Weiwei Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Craig Blackmore

[PATCH v6 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/trace-events| 12 + target/riscv/vector_helper.c | 95 +--- 2 files changed

[PATCH v6 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

...@embecosm.com/ - v5: https://lore.kernel.org/all/20241211143118.661268-1-craig.blackm...@embecosm.com/ Cc: Richard Henderson Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: Weiwei Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Craig

[PATCH v8 1/2] target/riscv: rvv: fix typo in vext continuous ldst function names

Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85dd1d200..0f57e48cc5 100644 --- a/target/riscv

[PATCH v8 2/2] target/riscv: rvv: speed up small unit-stride loads and stores

Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore

[PATCH v8 0/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores

Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Cc: Paolo Savini Craig Blackmore (2): target/riscv: rvv: fix typo in vext continuous ldst function names target/riscv: rvv: speed up small unit-stride loads and stores target/riscv/vector_helper.c | 26 +- 1 file changed,

[RFC PATCH v5 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/trace-events| 12 + target/riscv/vector_helper.c | 95 +--- 2 files changed

[RFC PATCH v5 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Craig Blackmore (1): target/riscv: rvv: Use wider accesses for unit stride load/store target/riscv/trace-events| 12 + target/riscv/vector_helper.c | 95

[PATCH v7 2/2] target/riscv: rvv: speed up small unit-stride loads and stores

Calling `vext_continuous_ldst_tlb` for load/stores smaller than 12 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore

[PATCH v7 1/2] target/riscv: rvv: fix typo in vext continuous ldst function names

Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85dd1d200..0f57e48cc5 100644 --- a/target/riscv

[PATCH v7 0/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores

stair Francis Cc: Bin Meng Cc: Weiwei Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Cc: Paolo Savini Craig Blackmore (2): target/riscv: rvv: fix typo in vext continuous ldst function names target/riscv: rvv: speed up small unit-stride load