[PATCH v2] linux-user/riscv: Add Zicboz extensions to hwprobe

From: Christoph Müllner Upstream Linux recently added RISC-V Zicboz support to the hwprobe API. This patch introduces this for QEMU's user space emulator. Signed-off-by: Christoph Müllner --- linux-user/syscall.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/syscall.c b/lin

[PATCH] linux-user/riscv: Add Zicboz extensions to hwprobe

From: Christoph Müllner Upstream Linux recently added RISC-V Zicboz support to the hwprobe API. This patch introduces this for QEMU's user space emulator. Signed-off-by: Christoph Müllner --- linux-user/syscall.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/syscall.c b/lin

[RFC PATCH 1/2] RISC-V: Add support for Ztso

From: Palmer Dabbelt The Ztso extension is already ratified, this adds it as a CPU property and adds various fences throughout the port in order to allow TSO targets to function on weaker hosts. We need no fences for AMOs as they're already SC, the placess we need barriers are described. These f

[RFC PATCH 0/2] RISC-V: Add TSO extensions (Ztso/Ssdtso)

From: Christoph Müllner This series picks up an earlier v2 Ztso patch from Palmer and adds a second to support Ssdtso. Palmer's v2 Ztso patch can be found here: https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-pal...@rivosinc.com/ This patch did not apply cleanly b

[RFC PATCH 2/2] RISC-V: Add support for Ssdtso

From: Christoph Müllner The Ssdtso extension introduces a DTSO field to the {m,s,h}envcfg register to enable TSO at run-time. Building on top of Ztso support, this patch treates Ssdtso just like Ztso (always execute in TSO mode), which should be fine from a correctness perspective. Similar like

[PATCH] riscv/disas: Fix disas output of upper immediates

From: Christoph Müllner The GNU assembler produces the following output for instructions with upper immediates: 2597auipc a1,0x2 24b7lui s1,0x2 6409lui s0,0x2 # c.lui The immediate operands of upper immediates are

[PATCH v8] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (M

[PATCH v7] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (M

[PATCH v6] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (M

[PATCH v5] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (M

[PATCH v4 2/3] target/riscv: Use float64_to_int64_modulo for fcvtmod.w.d

From: Christoph Müllner For the most part we can use the new generic routine, though exceptions need some post-processing. Signed-off-by: Christoph Müllner --- target/riscv/fpu_helper.c | 78 ++- 1 file changed, 27 insertions(+), 51 deletions(-) diff --git

[PATCH v4 1/3] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Mod

[PATCH v4 3/3] DO NOT MERGE: tests/tcg/riscv64: Add test for fcvtmod.w.d

From: Christoph Müllner This patch introduces a test for Zfa's fcvtmod.w.d instruction. The test cases test for correct results and flag behaviour. Note, that the Zfa specification requires fcvtmod's flag behaviour to be identical to a fcvt with the same operands (which is also tested). DO NOT M

[PATCH v4 0/3] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex The Zfa specifciation is frozen and is in public review since May 3, 2023: https://groups.google.com/a/groups.ris

[PATCH v2 8/8] disas/riscv: Add support for XThead* instructions

From: Christoph Müllner Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- disas/meson.build | 1 + di

[PATCH v2 7/8] disas/riscv: Add support for XVentanaCondOps

From: Christoph Müllner This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- disas/meson.build | 5 - disas/riscv-xventana.c | 41 + di

[PATCH v2 0/8] disas/riscv: Add vendor extension support

From: Christoph Müllner This series adds vendor extension support to the QEMU disassembler for RISC-V. The following vendor extensions are covered: * XThead{Ba,Bb,Bs,Cmo,CondMov,FMemIdx,Fmv,Mac,MemIdx,MemPair,Sync} * XVentanaCondOps So far, there have been two attempts to add vendor extension su

[PATCH v2 5/8] disas/riscv: Encapsulate opcode_data into decode

From: Christoph Müllner This patch adds a reference to a struct rv_opcode_data object into struct rv_decode. This further allows to remove all references to the global variable opcode_data (which is renamed to rvi_opcode_data). This patch does not introduce any functional change, but prepares th

[PATCH v2 3/8] disas/riscv: Move types/constants to new header file

From: Christoph Müllner In order to enable vendor disassembler support, we need to move types and constants into a header file so that other compilation units can use them as well. This patch does not introduce any functional changes. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Sign

[PATCH v2 1/8] target/riscv: Use xl instead of mxl for disassemble

From: LIU Zhiwei Disassemble function(plugin_disas, target_disas, monitor_disas) will always call set_disas_info before disassembling instructions. plugin_disas and target_disas will always be called under a TB, which has the same XLEN. We can't ensure that monitor_disas will always be called

[PATCH v2 4/8] disas/riscv: Make rv_op_illegal a shared enum value

From: Christoph Müllner The enum value 'rv_op_illegal' does not represent an instruction, but is a catch-all value in case we have no match in the decoder. Let's make the value a shared one, so that other compile units can reuse it. Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Signed-

[PATCH v2 2/8] target/riscv: Factor out extension tests to cpu_cfg.h

From: Christoph Müllner This patch moves the extension test functions that are used to gate vendor extension decoders, into cpu_cfg.h. This allows to reuse them in the disassembler. This patch does not introduce new functionality. However, the patch includes a small change: The parameter for the

[PATCH v2 6/8] disas/riscv: Provide infrastructure for vendor extensions

From: Christoph Müllner A previous patch provides a pointer to the RISCVCPUConfig data. Let's use this to add the necessary code for vendor extensions. This patch does not change the current behaviour, but clearly defines how vendor extension support can be added to the disassembler. Reviewed-by

[PATCH 0/9] disas/riscv: Add vendor extension support

From: Christoph Müllner This series adds vendor extension support to the QEMU disassembler for RISC-V. The following vendor extensions are covered: * XThead{Ba,Bb,Bs,Cmo,CondMov,FMemIdx,Fmv,Mac,MemIdx,MemPair,Sync} * XVentanaCondOps So far, there have been two attempts to add vendor extension su

[PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode

From: Christoph Müllner This patch adds a reference to a struct rv_opcode_data object into struct rv_decode. This further allows to remove all references to the global variable opcode_data (which is renamed to rvi_opcode_data). This patch does not introduce any functional change, but prepares th

[PATCH 8/9] disas/riscv: Add support for XVentanaCondOps

From: Christoph Müllner This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- disas/meson.build | 5 - disas/riscv-xventana.c | 41 + disas/riscv-xventana.h | 18 ++

[PATCH 3/9] disas/riscv: Move types/constants to new header file

From: Christoph Müllner In order to enable vendor disassembler support, we need to move types and constants into a header file so that other compilation units can use them as well. This patch does not introduce any functional changes. Signed-off-by: Christoph Müllner --- disas/riscv.c | 270 +

[PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h

From: Christoph Müllner The file target/riscv/cpu.h cannot be included by files outside of target/riscv/. To share data with other parts of QEMU (e.g. the disassembler) we need to factor out the relevant code. Therefore, this patch moves the definition of RISCVCPUConfig (and tightly coupled depen

[PATCH 9/9] disas/riscv: Add support for XThead* instructions

From: Christoph Müllner Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- disas/meson.build | 1 + disas/riscv-xthead.c |

[PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

From: Christoph Müllner The disassembler needs the available extensions in order to properly decode instructions in case of overlapping encodings (e.g. for vendor extensions). Let's use the field 'disassemble_info::private_data' to store our RISCVCPUConfig pointer. Signed-off-by: Christoph Müll

[PATCH 7/9] disas/riscv: Provide infrastructure for vendor extensions

From: Christoph Müllner A previous patch provides a pointer to the RISCVCPUConfig data. Let's use this to add the necessary code for vendor extensions. This patch does not change the current behaviour, but clearly defines how vendor extension support can be added to the disassembler. Signed-off-

[PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value

From: Christoph Müllner The enum value 'rv_op_illegal' does not represent an instruction, but is a catch-all value in case we have no match in the decoder. Let's make the value a shared one, so that other compile units can reuse it. Signed-off-by: Christoph Müllner --- disas/riscv.c | 2 +- di

[PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble

From: LIU Zhiwei Disassemble function(plugin_disas, target_disas, monitor_disas) will always call set_disas_info before disassembling instructions. plugin_disas and target_disas will always be called under a TB, which has the same XLEN. We can't ensure that monitor_disas will always be called

[RFC PATCH v3] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Mod

[RFC PATCH v2] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Mod

[PATCH] riscv: Add support for the Zfa extension

From: Christoph Müllner This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Mod

[PATCH] disas/riscv: Add support for XThead* instructions

From: Christoph Müllner Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- disas/riscv.c | 366 ++

[PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair

From: Christoph Müllner The XTheadMemPair does not define any restrictions for store-pair instructions (th.sdd or th.swd). However, the current code enforces the restrictions that are required for load-pair instructions. Let's fix this by removing this code. Signed-off-by: Christoph Müllner ---

[PATCH v5 13/14] RISC-V: Adding XTheadFmv ISA extension

From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/

[PATCH v5 11/14] RISC-V: Set minimum priv version for Zfh to 1.11

From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- ta

[PATCH v5 09/14] RISC-V: Adding T-Head MemIdx extension

From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single

[PATCH v5 12/14] RISC-V: Add initial support for T-Head C906

From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- C

[PATCH v5 10/14] RISC-V: Adding T-Head FMemIdx extension

From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use singl

[PATCH v5 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support

--git a/MAINTAINERS b/MAINTAINERS index c581c11a64..9dc0a2954e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-ri...@nongnu.org +S

[PATCH v5 08/14] RISC-V: Adding T-Head MemPair extension

From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Christoph Müllner --- Changes in v2: - Add

[PATCH v5 04/14] RISC-V: Adding XTheadBb ISA extension

From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA

[PATCH v5 07/14] RISC-V: Adding T-Head multiply-accumulate instructions

From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single de

[PATCH v5 05/14] RISC-V: Adding XTheadBs ISA extension

From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA

[PATCH v5 02/14] RISC-V: Adding XTheadSync ISA extension

From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-develop

[PATCH v5 01/14] RISC-V: Adding XTheadCmo ISA extension

coders[] = { { always_true_p, decode_insn32 }, +{ has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 00..30533a66f5 --- /de

[PATCH v5 06/14] RISC-V: Adding XTheadCondMov ISA extension

From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix inval

[PATCH v5 00/14] Add support for the T-Head vendor extensions

From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSyn

[PATCH v5 03/14] RISC-V: Adding XTheadBa ISA extension

CATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright

[PATCH v4 10/14] RISC-V: Adding T-Head FMemIdx extension

From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use singl

[PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension

From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use singl

[PATCH v4 02/14] RISC-V: Adding XTheadSync ISA extension

From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-develop

[PATCH v4 04/14] RISC-V: Adding XTheadBb ISA extension

From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA

[PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions

From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single de

[PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support

--git a/MAINTAINERS b/MAINTAINERS index c581c11a64..9dc0a2954e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-ri...@nongnu.org +S

[PATCH v4 11/14] RISC-V: Set minimum priv version for Zfh to 1.11

From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- ta

[PATCH v4 06/14] RISC-V: Adding XTheadCondMov ISA extension

From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix inval

[PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension

From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/

[PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension

From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single

[PATCH v4 12/14] RISC-V: Add initial support for T-Head C906

From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- C

[PATCH v4 05/14] RISC-V: Adding XTheadBs ISA extension

From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA

[PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension

coders[] = { { always_true_p, decode_insn32 }, +{ has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 00..30533a66f5 --- /de

[PATCH v4 00/14] Add support for the T-Head vendor extensions

From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSyn

[PATCH v4 03/14] RISC-V: Adding XTheadBa ISA extension

CATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright

[PATCH v3 03/14] RISC-V: Adding XTheadBa ISA extension

CATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright

[PATCH v3 04/14] RISC-V: Adding XTheadBb ISA extension

From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA

[PATCH v3 12/14] RISC-V: Add initial support for T-Head C906

From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- C

[PATCH v3 06/14] RISC-V: Adding XTheadCondMov ISA extension

From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix inval

[PATCH v3 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support

--git a/MAINTAINERS b/MAINTAINERS index 6982be48c6..f16916fd07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-ri...@nongnu.org +S

[PATCH v3 11/14] RISC-V: Set minimum priv version for Zfh to 1.11

From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- ta

[PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension

From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/

[PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension

From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use singl

[PATCH v3 02/14] RISC-V: Adding XTheadSync ISA extension

From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-develop

[PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension

From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single

[PATCH v3 05/14] RISC-V: Adding XTheadBs ISA extension

From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA

[PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension

From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use singl

[PATCH v3 00/14] Add support for the T-Head vendor extensions

From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSyn

[PATCH v3 01/14] RISC-V: Adding XTheadCmo ISA extension

, decode_insn32 }, +{ has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 00..30533a66f5 --- /dev/null +++ b/target/riscv/xthead.decod

[PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions

From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single de

[PATCH v2 03/15] RISC-V: Adding XTheadBa ISA extension

/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright (c) 2022 Christoph Muellner, christop

[PATCH v2 04/15] RISC-V: Adding XTheadBb ISA extension

From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Make implementation compatible with RV32. - Use single decode

[PATCH v2 08/15] RISC-V: Adding T-Head MemPair extension

From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses Co-developed-by: LIU Z

[PATCH v2 07/15] RISC-V: Adding T-Head multiply-accumulate instructions

From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- t

[PATCH v2 13/15] RISC-V: Add initial support for T-Head C906

From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner Changes in v2: - Drop C910 as it do

[PATCH v2 12/15] RISC-V: Set minimum priv version for Zfh to 1.11

From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 +- 1 f

[PATCH v2 00/15] Add support for the T-Head vendor extensions

From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSyn

[PATCH v2 15/15] target/riscv: add a MAINTAINERS entry for XThead* extension support

index b270eb8e5b..38f3ab3772 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -294,6 +294,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-ri...@nongnu.org +S: Supported +F: target/riscv

[PATCH v2 14/15] RISC-V: Adding XTheadFmv ISA extension

From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h

[PATCH v2 02/15] RISC-V: Adding XTheadSync ISA extension

From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Changes in

[PATCH v2 09/15] RISC-V: Adding T-Head MemIdx extension

From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Avoid signed-bitfield-extraction by using signed immediate field

[PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension

{ always_true_p, decode_insn32 }, +{ has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 00..30533a66f5 --- /dev/null +++ b/target/riscv/

[PATCH v2 11/15] RISC-V: Adding T-Head XMAE support

From: Christoph Müllner This patch adds support for the T-Head specific extended memory attributes. Similar like Svpbmt, this support does not have much effect as most behaviour is not modelled in QEMU. We also don't set any EDATA information, because XMAE discovery is done using the vendor ID i

[PATCH v2 06/15] RISC-V: Adding XTheadCondMov ISA extension

From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix invalid use of register from dest_gpr() - Use single decoder for XThead extensions Co-developed-by: LI

[PATCH v2 10/15] RISC-V: Adding T-Head FMemIdx extension

From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_th_address_indexed for address calculations Co-develope

[PATCH v2 05/15] RISC-V: Adding XTheadBs ISA extension

From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions Co-developed-by: Ph

[RFC PATCH] RISC-V: Save mmu_idx using FIELD_DP32 not OR

From: Christoph Müllner Setting flags using OR might work, but is not optimal for a couple of reasons: * No way grep for stores to the field MEM_IDX. * The return value of cpu_mmu_index() is not masked (not a real problem as long as cpu_mmu_index() returns only valid values). * If the offset of

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