[PATCH v2] tests/qtest: Fix npcm7xx_timer-test.c flaky test

npcm7xx_timer-test occasionally fails due to the state of the timers from the previous test iteration. Advancing the clock step after the reset resolves this issue. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897 Signed-off-by: Chris Rauer --- tests/qtest/npcm7xx_timer-test.c | 1

Re: [PATCH] tests/qtest: Fix npcm7xx_timer-test.c flaky test

Ack. will send out v2. On Wed, Sep 27, 2023 at 9:44 PM Thomas Huth wrote: > On 28/09/2023 05.45, Chris Rauer wrote: > > Could you please add a proper patch description how this is fixing the > issue? > > Thanks, >Thomas > > > > Fixes: https://gitlab.co

[PATCH] tests/qtest: Fix npcm7xx_timer-test.c flaky test

Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897 Signed-off-by: Chris Rauer --- tests/qtest/npcm7xx_timer-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/npcm7xx_timer-test.c b/tests/qtest/npcm7xx_timer-test.c index 43711049ca..58f58c2f71 100644 --- a/tests/qtest

Re: [PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

gt; https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg04903.html > > On Fri, Sep 22, 2023 at 11:14 AM Chris Rauer wrote: > >> The counter register is only 24-bits and counts down. If the timer is >> running but the qtimer to reset it hasn't fired off yet, there is a chanc

[PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

The counter register is only 24-bits and counts down. If the timer is running but the qtimer to reset it hasn't fired off yet, there is a chance the regster read can return an invalid result. Signed-off-by: Chris Rauer --- hw/timer/npcm7xx_timer.c | 3 +++ 1 file changed, 3 insertions(+)

[PATCH] hw/ssi: Fix Linux driver init issue with xilinx_spi

Register section: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf Signed-off-by: Chris Rauer --- hw/ssi/xilinx_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 552927622f

Re: [PATCH 0/2] Adds designware i2c module and adds it to virt arm

2 PM Philippe Mathieu-Daudé wrote: > +Enrico Weigelt > > On 26/1/22 19:03, Peter Maydell wrote: > > On Wed, 26 Jan 2022 at 17:12, Chris Rauer wrote: > >> > >>> I need to see a pretty strong justification for why we should be > >>> adding new kinds o

Re: [PATCH 0/2] Adds designware i2c module and adds it to virt arm

ndalone PCI I2C controllers. I’ve seen I2C controllers on PCI devices with other things but I don’t think those could be used for IPMI SSIF or other general I2C use cases. Do you know of a particular device I should take a look at? -Chris On Wed, Jan 26, 2022 at 10:03 AM Peter Maydell wrote: &

Re: [PATCH 0/2] Adds designware i2c module and adds it to virt arm

>I need to see a pretty strong justification for why we should be adding new kinds of devices to the virt machine, The designware i2c controller is a very common controller on many ARM SoCs. It has device tree bindings and ACPI bindings which makes it ideal for this platform. >Forgot to mention,

[PATCH v2] hw/arm: Add support for kudo-bmc board.

kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Since v1: - hyphenated Cortex-A9 Tested: Booted kudo firmware. Signed-off-by: Chris Rauer --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 34

[PATCH] hw/arm: Add support for kudo-bmc board.

kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Tested: Booted kudo firmware. Signed-off-by: Chris Rauer --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 34 ++ 2 files changed, 35