Hi all
Recently I am investigating is there better BT solution? I got two kinds of
popular method.
1. Qemu TCG-IR is offered by Qemu, translate all to op then to target
insn
2. With Qemu runtime information convert all insn to LLVM IR, then
with LLVM backend and kinds of opt o
Hi all
I've noticed that Qemu maintained the target arch register in memory for
capacity, but the load/store really cost a bit much, is there any way map
the register directly.
For example, in x86 to aarch64, x86 uses 8 registers mostly such eax ebx ecx
and so on, and aarch64 arch got 31 ge
Hi
I'm running SPEC CPU2006 on three kinds of situation, native aarch64 binary and
emulator x86_64 system running SPEC CPU2006 and linux user mode level running
x86_64 SPEC CPU2006 binary.
To find where the performance lose, translator ? or execution of instruction
after TCG? Or something else
Hi all
Anybody got some infos about gnemul? I've googled the internet, just some
pages about old and out of date versions about gnemul, and they are built
for ARM32, and I need gnemul for AARCH64, does anybody know how to build it?
Thanks
Chaos
On 29 May 2014 08:58, Chaos Shu wrote:
> 1. Any benchmarks paying attention to TCG code generate quality
> measured by code expansion ratio? Of course I’ve got some news said
> that the ratio maybe 4 or 5 in X86 to MIPS, that is to say 1 x86 insn
> to 4 or 5 mips insns, Does
Hi all
I'm new to the list, and recently I'm digging in Qemu's source code, I've
got something confused me much, simply list the items:
1. Any benchmarks paying attention to TCG code generate quality
measured by code expansion ratio? Of course I've got some news said that the
ratio ma
