RE: [EXTERNAL] Re: MIPS cache bypass on custom board

post (which describes exactly my problem. Thank you for finding that!) -Original Message- From: Philippe Mathieu-Daudé Sent: Friday, December 13, 2019 8:39 PM To: Bensch, Alexander ; qemu-devel@nongnu.org Cc: Peter Maydell ; Richard Henderson Subject: [EXTERNAL] Re: MIPS cache bypass on c

MIPS cache bypass on custom board

Sensitive Hi all, Currently stuck on a problem in QEMU 4.0.0. I'm trying to implement a custom device using a MIPS 24Kc CPU. The device boots from an SPI flash device that is mapped to 0x9F00 (physical address 0x1F00). I got the initial load and execute working by direct loading a flas

MIPS32 - 16550 UART implementation on custom board

Hi all, I'm trying to use QEMU to emulate a piece of firmware, but I'm having trouble getting the UART device to properly update the Line Status Register and display the input character. Details: Target device: Qualcomm QCA9533 (Documentation here if you're curious