Am 14.07.2015 um 19:49 schrieb Peter Maydell:
> On 7 July 2015 at 19:25, Alex Zuepke wrote:
>
> A commit message that wasn't just the one-line summary would
> be nice. Sometimes a patch really is trivial enough that it's
> not worth describing in more than just a single line, but
> those situatio
Am 07.07.2015 um 22:50 schrieb Peter Crosthwaite:
> On Tue, Jul 7, 2015 at 11:25 AM, Alex Zuepke
> wrote:
>>
>> Signed-off-by: Alex Zuepke
>> ---
>> hw/arm/armv7m.c | 17 -
>> target-arm/cpu.c|2 ++
>> target-arm/helper.c | 30 --
>> 3
Am 26.06.2015 um 16:04 schrieb Peter Maydell:
> Ping?
OK for me.
Best regards
Alex
>
> thanks
> -- PMM
>
> On 15 June 2015 at 19:49, Peter Maydell wrote:
>> This patchset makes the ARM and Thumb encodings of the YIELD hint
>> instruction in the ARM cause the TCG CPU to yield control back
>> t
Am 16.06.2015 um 13:53 schrieb Peter Maydell:
> On 16 June 2015 at 12:11, Alex Züpke wrote:
>> But the startup is not my problem, it's the later parts.
>
> But it was my problem because it meant your test case wasn't
> functional :-)
>
>> I added the WFE
Hi Peter,
Am 16.06.2015 um 12:59 schrieb Peter Maydell:
> On 16 June 2015 at 11:33, Peter Maydell wrote:
>> Pressing a key does not unwedge the test case for me.
>
> Looking at the logs, this seems to be expected given what
> the guest code does with CPU #1: (the below is edited logs,
> created
Am 15.06.2015 um 17:49 schrieb Peter Maydell:
> On 15 June 2015 at 16:36, Alex Züpke wrote:
>> So this is the way to go:
>>
>> --- a/target-arm/translate.c
>> +++ b/target-arm/translate.c
>> @@ -4084,6 +4084,7 @@ static void gen_nop_hint(DisasContext *s, int va
Am 15.06.2015 um 17:18 schrieb Peter Maydell:
> On 15 June 2015 at 16:07, Alex Züpke wrote:
>> Am 15.06.2015 um 17:04 schrieb Peter Maydell:
>>> On 12 June 2015 at 17:38, Alex Züpke wrote:
>>>> Hi,
>>>>
>>>> I'm benchmarking some IPI (=
Am 15.06.2015 um 17:04 schrieb Peter Maydell:
> On 12 June 2015 at 17:38, Alex Züpke wrote:
>> Hi,
>>
>> I'm benchmarking some IPI (== inter-processor-interrupt) synchronization
>> stuff of my custom kernel on QEMU ARM (qemu-system-arm -M vexpress-a15 -smp
Am 15.06.2015 um 16:51 schrieb Peter Maydell:
> On 15 June 2015 at 15:44, Alex Züpke wrote:
>> Am 12.06.2015 um 20:03 schrieb Peter Maydell:
>>> Probably the best approach would be to have something in
>>> arm_cpu_set_irq() which says "if we are CPU X and we'
Hi Peter,
Am 12.06.2015 um 20:03 schrieb Peter Maydell:
> On 12 June 2015 at 17:38, Alex Züpke wrote:
>> Hi,
>>
>> I'm benchmarking some IPI (== inter-processor-interrupt) synchronization
>> stuff of my custom kernel on QEMU ARM (qemu-system-arm -M vexpress-
Hi,
I'm benchmarking some IPI (== inter-processor-interrupt) synchronization stuff
of my custom kernel on QEMU ARM (qemu-system-arm -M vexpress-a15 -smp 2) and
ran into the following problem: pending IPIs are delayed until the QEMU main
loop receives an event (for example the timer interrupt ex
Add the missing 64-bit "MOV Ex, simm16" variant in RLC format.
Signed-off-by: Alex Zuepke
--
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 7aa6aed..a76a7e4 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -487,6 +487
Fixes offset masking for BOL opcodes and a typo (LONF -> LONG)
Signed-off-by: Alex Zuepke
--
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 65abf45..c132223 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3203,7 +3203,7 @@ static void deco
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