Greg Bellows writes:
> On 3 June 2014 05:21, Alex Bennée wrote:
>
>>
>> Edgar E. Iglesias writes:
>>
>> > From: "Edgar E. Iglesias"
>> >
>> > No functional change.
>> > Prepares for future additions of the EL2
+switch (op2_ll) {
> +case 1:
> +gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16));
> +break;
> +case 2:
> +if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_pl == 0) {
> +unallocated_encoding(s);
> +break;
> +}
> +tmp = tcg_const_i32(syn_aa64_hvc(imm16));
> +gen_a64_set_pc_im(s->pc);
> +gen_helper_hvc(cpu_env, tmp);
> +tcg_temp_free_i32(tmp);
> +break;
> +default:
> unallocated_encoding(s);
> break;
> }
> -gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16));
> break;
> case 1:
> if (op2_ll != 0) {
--
Alex Bennée
l[new_el] = env->exception.vaddress;
> qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
>env->cp15.far_el[new_el]);
> -break;
> case EXCP_BKPT:
> case EXCP_UDEF:
> case EXCP_SWI:
> + env-&
> +case EXCP_IRQ:
> +return ((IS_M(env) && env->regs[15] < 0xfff0)
> +|| !(env->daif & PSTATE_I));
> +default:
> +assert(0);
g_assert_not_reached() is clearer about the intent here.
> +break;
> +}
> +}
> +
> static inline CPUARMState *cpu_init(const char *cpu_model)
> {
> ARMCPU *cpu = cpu_arm_init(cpu_model);
--
Alex Bennée
1U << 10)
> +#define SCR_ST(1U << 11)
> +#define SCR_TWI (1U << 12)
> +#define SCR_TWE (1U << 13)
> +#define SCR_RES1_MASK (3U << 4)
> +#define SCR_RES0_MASK (0x3fff & ~SCR_RES1_MASK)
Again I have similar cognitive dissonance with the
tlb_flush(CPU(cpu), 1);
> +}
> +raw_write(env, ri, value);
> +}
> +
> static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
> +{ .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
> + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
> + .writefn = hcr_write },
> { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
>.type = ARM_CP_NO_MIGRATE,
>.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
--
Alex Bennée
gt; +{ .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
> + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3])
> },
> { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
>.type = ARM_CP_NO_MIGRATE,
>.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
--
Alex Bennée
;
> case EXCP_DATA_ABORT:
> env->cp15.esr_el[1] = env->exception.fsr;
> -env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,
> - env->exception.vaddress);
> +env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
> +env->exception.vaddress);
> qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
>(uint32_t)env->cp15.esr_el[1],
>(uint32_t)env->exception.vaddress);
--
Alex Bennée
