[0.00] fadump: Failed to find memory chunk for reservation!
And even with anything from 2GB - 19GB, the kernel fails to boot due to
some memory issues.
Trying with >20GB memory is recommended for now
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 49
During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger
MPIPL.
Currently QEMU treats it as "Unimplemented", handle the interrupts by
just logging that the interrupt happened.
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_sbe.c | 13 +
1 file changed, 13
Add offsets for the processor state captured during MPIPL dump.
This is incomplete. And might be implemented in future if the effort to
implement MPIPL is resumed again.
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_sbe.c | 27 +++
1 file changed, 27 insertions(+)
diff
ved the regions, and export /proc/vmcore, but
the vmcore won't have most basic kernel structures hence crash will be
unable to analyse the vmcore
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_sbe.c | 57
1 file changed, 57 insertions(+)
diff --git a/
Add the MDST, MDDT, MDRT tables offsets and structures as per current
skiboot upstream:
commit bc7b85db1e7e ("opal-ci: Remove centos7")
These structures will be later populated when preserving memory regions
for MPIPL
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_s
0 interrupt as pause_vcpus + guest_reset
See 'stopClocksS0' in SBE source code for more information.
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_sbe.c | 50 +++-
1 file changed, 41 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/pnv_sb
ccess relocated OPAL base address to get MDST, MDDT tables. Hence send
relocated base address to SBE via 'stash MPIPL config' chip-op. During
next
IPL SBE will send stashed data to hostboot... so that hostboot can access
these data.
Signed-off-by: Aditya Gupta
---
h
ive, which kernel then
exports in /proc/vmcore
Git Tree for Testing
https://github.com/adi-g15-ibm/qemu/tree/fadump-powernv-v1
Known Issues
* CPU save area has not been implemented
Aditya Gupta (7):
hw/ppc: Log S0/S1 Interrupt triggers by OPAL
hw/ppc: Implement S0 SBE interrupt as
estination address to where the memory is to be copied.
Implement the preserving/copying of the Real Mode Regions and the
Parameter Save Area in QEMU Pseries
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_rtas.c| 117 -
include/hw/ppc/spapr.h | 27 +
strictions on particular order of few registers, and is
free to be in any order for other registers.
Some registers mentioned in PAPR have not been exported as they are not
implemented in QEMU / don't make sense in QEMU.
Implement saving of CPU state according to the PAPR documen
Implement the handler for "ibm,configure-kernel-dump" rtas call in QEMU.
Currently the handler just does basic checks and handles
register/unregister/invalidate requests from kernel.
Fadump will be enabled in a later patch.
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_rtas
all registers
with the same value
* The implementation doesn't pass all the registers mentioned in PAPR since
QEMU doesn't implement them/doesn't need them.
The linux kernel uses only 9 of the 45 registers we are passing in QEMU.
Aditya Gupta (6):
hw/ppc: Implement skelet
PANIC: "Kernel panic - not syncing: sysrq triggered crash"
PID: 270
COMMAND: "sh"
TASK: c9e7cc00 [THREAD_INFO: c9e7cc00]
CPU: 3
STATE: TASK_RUNNING (PANIC)
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr
ing reboot (GUEST_RESET in QEMU doesn't clear
the memory)
Memory regions registered by fadump will be handled in a later patch.
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_rtas.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/hw/ppc/sp
ive of
whether it's a fadump boot or not, so that kernel can reserve memory to
store the firmware provided dump sections in case of a crash
Also, in case of a fadump boot, pass the fadump memory structure to the
kernel in "ibm,kernel-dump" device tree property.
Si
On 03/11/24 17:04, Nicholas Piggin wrote:
On Tue Aug 20, 2024 at 8:30 PM AEST, Aditya Gupta wrote:
Currently any device tree passed with -dtb option in QEMU, was ignored
by the PowerNV code.
Read and pass the passed -dtb to the kernel, thus enabling easier
debugging with custom DTBs.
The
Hi all,
Just a ping for this. Any comments ?
Thanks,
Aditya Gupta
On 20/08/24 16:00, Aditya Gupta wrote:
Currently any device tree passed with -dtb option in QEMU, was ignored
by the PowerNV code.
Read and pass the passed -dtb to the kernel, thus enabling easier
debugging with custom DTBs
Hi,
Seems there are more confusing option descriptions like:
+ printf "%s\n" ' --disable-install-blobs install provided firmware
blobs'
...
+ printf "%s\n" ' --disable-coroutine-pool coroutine freelist (better
performance)'
Should we change t
Hi Philippe,
Sorry for the late reply.
On 12/09/24 12:34, Philippe Mathieu-Daudé wrote:
Hi Aditya,
On 12/9/24 08:52, Aditya Gupta wrote:
Currently starting a pSeries machine, with lesser than 128MiB shows
below error:
qemu-system-ppc64: pSeries SLOF firmware requires >= 80ld
logic, the description should be 'Disable debug symbols...'
instead of 'Enable debug symbols...', Fix the typo by replacing Enable
with Disable.
Signed-off-by: Aditya Gupta
---
scripts/meson-buildoptions.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
value to use 'HWADDR_PRId', instead of
'HWADDR_PRIx' thus showing decimal value instead of hex.
Thus, change the message to below error:
qemu-system-ppc64: pSeries SLOF firmware requires >= 128MiB guest RMA (Real
Mode Area memory)
Signed-off-by: Aditya Gupta
---
This is an
Hi Amit,
On 02/09/24 11:19, Amit Machhiwal wrote:
On 2024/07/31 11:20 AM, Aditya Gupta wrote:
<...snip...>
Git Tree for Testing
QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-v6-pseries
Has been tested with following cases:
* '-M pseries' / '-M
Hi Amit,
On 29/08/24 17:49, Amit Machhiwal wrote:
Hi Aditya,
On 2024/07/31 11:20 AM, Aditya Gupta wrote:
Overview
Split "Power11 support for QEMU" into 2 patch series: pseries & powernv.
This patch series is for pseries support for Power11.
As Power11 core is s
Hi,
Any comments on this ?
Thanks,
Aditya Gupta
On 31/07/24 11:20, Aditya Gupta wrote:
Overview
Split "Power11 support for QEMU" into 2 patch series: pseries & powernv.
This patch series is for pseries support for Power11.
As Power11 core is same as Power10,
' is passed, it completely overrides any dtb nodes or
changes QEMU might have done, such as '-append' arguments to the kernel
(which are mentioned in /chosen/bootargs in the dtb), hence add warning
when -dtb is being used
Signed-off-by: Aditya Gupta
---
Changelog
===
v4:
+ use
on about CAS, I don't have idea on it, other
than the minimum basics. But thanks to you and Cedric, got to know
somethings.
Thanks,
Aditya Gupta
The other question... Some machines rebuild fdt at init, others at
reset time. As far as I understood, spapr has to rebuild on reset
becau
e little nit is MachineState.fdt vs PnvMachineState.fdt
which is now confusing. I would call the new PnvMachineState member
something like fdt_from_dtb, or fdt_override?
I agree. this is confusing. machine->fdt could be used instead ?
Sure, will use it.
Thanks,
Aditya Gupta
The othe
' is passed, it completely overrides any dtb nodes or
changes QEMU might have done, such as '-append' arguments to the kernel
(which are mentioned in /chosen/bootargs in the dtb), hence add warning
when -dtb is being used
Signed-off-by: Aditya Gupta
---
Changelog
===
v3:
+ use
Hi Cedric,
Sorry for the late reply.
On 01/08/24 15:22, Cédric Le Goater wrote:
On 8/1/24 10:51, Aditya Gupta wrote:
Currently any device tree passed with -dtb option in QEMU, was ignored
by the PowerNV code.
Read and pass the passed -dtb to the kernel, thus enabling easier
debugging with
' is passed, it completely overrides any dtb nodes or
changes QEMU might have done, such as '-append' arguments to the kernel
(which are mentioned in /chosen/bootargs in the dtb), hence add warning
when -dtb is being used
Signed-off-by: Aditya Gupta
---
Changelog
===
v2:
+ m
27;", machine->dtb);
+ exit(1);
+ }
We should try to report such errors earlier than in reset.
Thanks, I will remember this from next time.
Can you please introduce a PnvMachineState::dtb attribute and
initialize it
in pnv_init() after ->initrd_filename.
Sure, I w
' is passed, it completely overrides any dtb nodes or
changes QEMU might have done, such as '-append' arguments to the kernel
(which are mentioned in /chosen/bootargs in the dtb), hence add warning
when -dtb is being used
Signed-off-by: Aditya Gupta
---
Changelog
===
v1:
+ use
Hi Cedric,
On 24/07/31 04:43PM, Cédric Le Goater wrote:
> Hello Aditya,
>
> On 7/31/24 15:22, Aditya Gupta wrote:
> > Currently any device tree passed with -dtb option in QEMU, was ignored
> > by the PowerNV code.
> >
> > Read and pass the passed -dtb to
Hi Daniel,
Thank you for the review.
On 24/07/31 02:34PM, Daniel P. Berrangé wrote:
> On Wed, Jul 31, 2024 at 06:52:35PM +0530, Aditya Gupta wrote:
> > Currently any device tree passed with -dtb option in QEMU, was ignored
> > by the PowerNV code.
> >
> > Read and
' is passed, it completely overrides any dtb nodes or
changes QEMU might have done, such as '-append' arguments to the kernel
(which are mentioned in /chosen/bootargs in the dtb), hence add warning
when -dtb is being used
Signed-off-by: Aditya Gupta
---
This is an RFC patch, an
reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (4):
target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'
target/ppc
added.
Remove the duplicate code and share using common macros.
Reviewed-by: Nicholas Piggin
Signed-off-by: Harsh Prateek Bora
[adityag: renamed many POWERPC_* flags to PPC_* flags, checkpatch fixes]
Signed-off-by: Aditya Gupta
---
target/ppc/cpu_init.c | 124
-off-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 17 +
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..bbc51aa7fcdb 100644
--- a/docs/system/ppc
egressions with
compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 4 +++
Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/compat.c | 7 +
target/ppc/cpu-models.c | 3 ++
target/ppc/cpu-models.h | 3 ++
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c| 60
target/ppc
Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/compat.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index ebef2cccecf3..5b20fd7ef04c 100644
-
added.
Remove the duplicate code and share using common macros.
Reviewed-by: Nicholas Piggin
Signed-off-by: Harsh Prateek Bora
[PMM: renamed many POWERPC_* flags to PPC_* flags, checkpatch fixes]
Signed-off-by: Aditya Gupta
---
target/ppc/cpu_init.c | 124
Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/compat.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index ebef2cccecf3..5b20fd7ef04c 100644
-
-off-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 17 +
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..bbc51aa7fcdb 100644
--- a/docs/system/ppc
Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/compat.c | 7 +
target/ppc/cpu-models.c | 3 ++
target/ppc/cpu-models.h | 3 ++
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c| 60
target/ppc
egressions with
compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 4 +++
default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (4):
target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'
target/ppc: Fix regression due to Power10 and Power11 having same PCR
target/ppc
e used in header files like
this to make up some complex flags.
In above case, `PPC_INSNS_FLAGS_POWER9` and `PPC_INSNS_BASE` seem
somewhat similar to me, but are very different considering the values.
What do you think ?
- Aditya Gupta
On 23/07/24 10:52, Nicholas Piggin wrote:
On Thu J
C_FLAGS_COMMON \
POWERPC_FLAG_POWER9
Can we keep PPC_FLAG_POWER9 here ?
Like if all PowerPC flags start with PPC_* ?
Thanks,
Aditya Gupta
+POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+POWERPC_FLAG_PMM | POWERP
Hi Harsh,
Is it okay if I do, the changes in your patch ?
Thanks,
Aditya Gupta
On 23/07/24 10:52, Nicholas Piggin wrote:
On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote:
From: Harsh Prateek Bora
Power9/10 initialization code consists of a lot of logical OR of
various flag bits
On 23/07/24 10:43, Nicholas Piggin wrote:
On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote:
Introduce 'PnvChipClass::logical_pvr' to know corresponding logical PVR
of a PowerPC CPU.
This helps to have a one-to-one mapping between PVR and logical PVR for
a CPU, and used
On 23/07/24 10:28, Nicholas Piggin wrote:
On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote:
Power11 has the same PCR (Processor Compatibility Register) value, as
Power10.
Due to this, QEMU considers Power11 as a valid compat-mode for Power10,
ie. earlier it was possible to run QEMU
On 23/07/24 09:51, Nicholas Piggin wrote:
On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote:
From: Harsh Prateek Bora
Power9/10 initialization code consists of a lot of logical OR of
various flag bits as supported by respective Power platform during its
initialization, most of which
e in bike shed painting. The
functionality of the patch looks okay.
I am okay if you want to do it, or i can do it in a separate follow up
patch.
Reviewed-by: Nicholas Piggin
Thanks for the tag Nick !
- Aditya Gupta
+
+pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
Hi Nick,
On 23/07/24 09:48, Nicholas Piggin wrote:
On Mon Jul 22, 2024 at 7:17 PM AEST, Aditya Gupta wrote:
Hello,
Any comments on this change ?
Though this isn't urgent and won't change behaviour much, mainly other
than skiboot recognising the chip as P10 DD2.
Hey Aditya,
Yea
Hello,
Any comments on this change ?
Though this isn't urgent and won't change behaviour much, mainly other
than skiboot recognising the chip as P10 DD2.
Thanks
- Aditya Gupta
On 02/05/24 13:51, Cédric Le Goater wrote:
On 5/2/24 08:27, Aditya Gupta wrote:
Power10 DD1.0 was
Any comments on this ?
This series is containing only the pseries support for Power11, hence
independent of skiboot patches. powernv is on hold till skiboot changes
are released.
Thanks,
Aditya Gupta
On 06/06/24 17:46, Aditya Gupta wrote:
Overview
Split "Power11 su
11's instance_init.
Also, I have applied Harsh's patch that should simplify the rest of the
patches.
Thanks,
Aditya Gupta
On 06/06/24 17:46, Aditya Gupta wrote:
Overview
Split "Power11 support for QEMU" into 2 patch series: pseries & powernv.
This
Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/compat.c | 7 ++
target/ppc/cpu-models.c | 3 +++
target/ppc/cpu-models.h | 3 +++
target/ppc/cpu_init.c | 54 +
4 files changed, 67 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc
sions with compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 5 +
2 files changed, 6 insertions(+)
di
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (4):
target/ppc: Add Power11 DD2.0 processor
ppc/pseries: Add Power11 cpu type
target/ppc: Introduce 'PowerPCCPUClass::logi
Piggin
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 17 +
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index
From: Harsh Prateek Bora
Power9/10 initialization code consists of a lot of logical OR of
various flag bits as supported by respective Power platform during its
initialization, most of which is duplicated and only selected bits are
added or removed as needed with each new platform support being a
Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/compat.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index 12dd8ae290ca..168a3c06316f 100644
--- a/target/ppc/compat.c
+++ b
Hello Nick,
On Wed, May 29, 2024 at 10:16:58AM GMT, Nicholas Piggin wrote:
> On Tue May 28, 2024 at 5:15 PM AEST, Cédric Le Goater wrote:
> > On 5/28/24 09:05, Aditya Gupta wrote:
> > > Skiboot/OPAL patches are in discussion upstream [1], with corresponding
> > > comm
Hello Harsh,
On Thu, May 30, 2024 at 10:57:31AM GMT, Harsh Prateek Bora wrote:
> Hi Aditya,
>
> On 5/28/24 12:35, Aditya Gupta wrote:
> > Add CPU target code to add support for new Power11 Processor.
> >
> > Power11 core is same as Power10, hence reuse functi
Hello Cedric,
Thanks for your reviews.
On Tue, May 28, 2024 at 09:40:12AM GMT, Cédric Le Goater wrote:
> Hello Aditya
>
> On 5/28/24 09:05, Aditya Gupta wrote:
> > Power11 core is same as Power10, use the existing functionalities to
> > introduce a Power11 chip and machine,
Hello Cedric,
On Tue, May 28, 2024 at 09:15:29AM GMT, Cédric Le Goater wrote:
> On 5/28/24 09:05, Aditya Gupta wrote:
> > Skiboot/OPAL patches are in discussion upstream [1], with corresponding
> > commits in github repository [2].
> >
> > Update skiboot.
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
: Aditya Gupta
---
docs/system/ppc/pseries.rst | 6 +++---
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs
onkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
Multiple alternative approaches were tried to fix this:
1. New PCR for Power11: No
2. 'Hacky fix': chose (n-1) entry in compat table in case of Power10.
Commit:
ht
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
stream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (11):
ppc: Add Power11 DD2.0 processor
ppc/pseries: Add Power11 cpu type
target/ppc: Introduce 'PowerPCCPUClass::logical_pvr'
target/ppc: Fix regression due to Powe
: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +--
hw/ppc/pnv.c| 120 ++--
hw/ppc/pnv_core.c | 11
include/hw/ppc/pnv.h| 5 ++
include/hw/ppc/pnv_chip.h | 7 +++
include/hw/ppc/pnv_core.h
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
sions with compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/target/ppc/cpu.
: Aditya Gupta
---
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 3 ++
target/ppc/cpu-models.h | 3 ++
target/ppc/cpu_init.c | 102
4 files changed, 115 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index
On Mon, May 27, 2024 at 05:15:05PM GMT, Cédric Le Goater wrote:
> On 5/27/24 09:10, Aditya Gupta wrote:
> > Power11 core is same as Power10, use the existing functionalities to
> > introduce a Power11 chip and machine, with Power10 chip as parent of
> > Power11 chip, thus
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
- remove commit to make Power11 as default
v2:
+ split powernv patch into homer,lpc,occ,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update sk
onkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
Multiple alternative approaches were tried to fix this:
1. New PCR for Power11: No
2. 'Hacky fix': chose (n-1) entry in compat table in case of Power10.
Commit:
ht
: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +--
hw/ppc/pnv.c| 119 ++--
hw/ppc/pnv_core.c | 11
include/hw/ppc/pnv.h| 5 ++
include/hw/ppc/pnv_chip.h | 7 +++
include/hw/ppc/pnv_core.h
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-
: Aditya Gupta
---
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 3 ++
target/ppc/cpu-models.h | 3 ++
target/ppc/cpu_init.c | 102
4 files changed, 115 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index
sions with compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/target/ppc/cpu.
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
: Aditya Gupta
---
docs/system/ppc/pseries.rst | 6 +++---
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs
e(&address_space_memory,
ADI_REGION_BASE, &xlat, &l, false, MEMTXATTRS_UNSPECIFIED);
or
+ cpu_physical_memory_read(ADI_REGION_BASE, &val, 4);
1st should return your MemoryRegion, and second one should call your
.read callback.
Thanks,
Aditya Gupta
On 03/05/24 10:22, Nicholas Piggin wrote:
On Sat Apr 27, 2024 at 12:32 AM AEST, Cédric Le Goater wrote:
On 4/26/24 13:00, Aditya Gupta wrote:
Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
with Power11 being the newest supported Power process
: Nicholas Piggin
Cc: Paolo Bonzini
Cc: Thomas Huth
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c| 2 +-
tests/qtest/pnv-xscom.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec76..06a4e4d13948 100644
--- a/hw/ppc/pnv.
parate patch ?
Thanks,
Aditya Gupta
Thanks,
- Aditya Gupta
C.
Hello David,
On 29/04/24 07:14, David Gibson wrote:
On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric le Goater wrote:
On 4/26/24 13:00, Aditya Gupta wrote:
Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
with Power11 being the newest supporte
pass
type_name as "power11" vs "power10".
Do the Power11 and Power10 processors have the same XSCOM and MMIO
address spaces ?
Yes. Hence using the same base and sizes.
Thanks,
Aditya Gupta
Will do it.
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
@
v3.
Skiboot reports :
[ 0.121234172,6] P11 DD1.00 detected
It is a DD2.0, with major revision = 0x2, and minor revision = 0. Might
need some change in skiboot. Will post a v3 series with changes.
Thanks,
- Aditya Gupta
C.
e that 'chipTOD' was added in commit 9a69950feb098. I2C mentions
> > yet to merge, is it merged yet ?
>
> yes.
Thanks for confirming Cédric !
- Aditya Gupta
>
> >
> > I will check whether this needs updating, but might do it in a separate
> > patch than this series.
>
> Thanks,
>
>
On Fri, Apr 26, 2024 at 04:38:13PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Skiboot/OPAL patches are in discussion upstream [1], with corresponding
> > commits in github repository [2].
> >
> > Update skiboot.lid, with binary built fro
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